Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
1999-10-29
2001-07-31
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S688000, C257S692000, C257S698000, C257S720000, C438S126000
Reexamination Certificate
active
06268648
ABSTRACT:
TECHNICAL FIELD
This invention is related to a substrate for mounting a semiconductor chip (called semiconductor chip package substrate hereafter), a method of fabricating the semiconductor chip package substrate, and a semiconductor device comprising the semiconductor chip package substrate onto which the semiconductor chip is mounted.
BACKGROUND ART
There is a growing need for a smaller semiconductor device package with multiple terminal pins due to increases of an integration rate and an operation frequency in the recent semiconductor device. However, a package size of a conventional peripheral terminal type utilizing a lead-frame has to be made larger if a number of the terminals should be increased further. One of countermeasures is to decrease a terminal pitch in the package. However, it is difficult to make the terminal pitch narrower than 0.4 mm.
To accommodate such increasing number of the terminals, an area array type package with its terminals disposing over a surface plane is introduced. The area array type package requires to have a wiring substrate for providing wiring from chip terminals to external terminal electrodes. The chip may be mounted either at the upper surface or the lower surface of the wiring substrate when the external terminal electrodes are disposed at the lower surface of the wiring substrate. When the chip is mounted on the upper surface of the wiring substrate, interlayer connections between the upper surface and the lower surface of the wiring substrate have to be provided. When the chip is mounted on the lower surface of the wiring substrate, the interlayer connections will not be required. However, a hollow space has to be provided to absorb total thickness of the chip and its sealing material when the chip is mounted on the lower surface of the wiring substrate.
The hollow space is called a cavity, and a structure with the cavity at the lower surface of the wiring substrate is called a cavity down structure. Typically, the structure can be made by hollowing out a substrate, or by making a hole through the substrate and adhering a base plate thereto. Wiring for a multiple layer structure is required when heights of chip bonding portions and external electrodes are changed because the wiring is also disposed on the same surface in this structure. According to the methods described above, a wiring structure, which satisfies required conditions for a three dimensional spatial relationships among the chip mount portion, the chip bonding portion and the external electrode portion.
One of the area array type semiconductor package is Ball Grid Array (BGA) in which solder balls are used as connection terminals. Cost of the BGA is higher than that of a semiconductor device fabricated with a conventional leadframe, and reduction of the cost is anticipated. The higher cost is due to a fact that a structure and fabricating process of the semiconductor chip package substrate are more complex than that of a substrate with the leadframe. Accordingly, it is anticipated the development of simpler structure and fabricating process of the semiconductor chip package substrate.
The wiring substrate used for the area array type semiconductor package is typically called an interposer. The interposer may be roughly classified into a film type and a rigid type. A number of the wiring layers can be either one, or two, or three and more layers. Generally, the fabricating cost is lower for a fewer number of the wiring layers.
The lowest cost is expected with the single layer wiring structure. If the wiring is disposed at least in both surfaces of the interposer, the semiconductor chip mount portion and the external terminals may be divided at the upper and the lower surfaces. However, the semiconductor chip mount portion and the external terminals are disposed on the same surface of the interposer with the single layer wiring structure. In such a single layer wiring structure, it is required to have the cavity portion on the wiring surface with a depth at least comparable to a thickness of the chip so as to store the chip therein. A method of fabricating such a cavity portion has become an important subject.
In the interposer so called TAB (Tape Automated Bonding) or TCP (Tape Carrier Package) and their packaging technology, the center portion of the interposer is bored through to store the semiconductor chip. With the rigid plate, the center portion of the interposer is similarly bored through to hollow the semiconductor chip store portion out and adhere a metal plate as the base plate thereto, or the cavity portion is fabricated at the center portion of the interposer. The wiring is disposed only in a flat plane portion, not inside the cavity portion.
DISCLOSURE OF INVENTION
The present invention is made by considering the above mentioned subjects. An object of the present invention is to provide a semiconductor chip package substrate for mounting a semiconductor chip(s) and a method of fabricating the semiconductor chip package substrate, and a semiconductor device wherein a semiconductor chip(s) is mounted on the semiconductor chip package substrate, those of which enable to reduce the size, increase the reliability, reduce the cost, and make the standardization of design and fabricating method easier.
The above object of the present invention is accomplished by a semiconductor chip package substrate with a cavity portion, or a semiconductor device fabricated by mounting at least one semiconductor chip in the cavity portion and sealing with plastic sealant, wherein said semiconductor chip package substrate comprises wiring disposed along a surface of the substrate and wall surfaces of the substrate in the cavity portion, the wiring comprises an external connection terminal portion for connecting to external connection terminals which are provided on the surface of the substrate at a side of the cavity portion's opening, an internal connection terminal portion for connecting to the mounted semiconductor chip, and a wiring portion disposed in between the external connection terminal portion and the internal connection terminal portion, the wiring portion is buried in a surface of the substrate and one of said wall surfaces of the substrate in the cavity portion and the internal connection terminal portion is disposed inside of the cavity portion.
For example, the wall surface of the substrate in the cavity portion may be extended toward the bottom surface of the cavity portion with a slant angle which is set within a predetermined angle range. Concretely, the slant angle may be within a range of 5-40°, and preferably within a range of 10-40°. The slant structure may be fabricated so as that a ratio L/G is within a range of 1.5<L/G<10, where G is a height of the slant structure of the wall surface of the substrate in the cavity portion, and L is its horizontal dimension. More preferable range of the ratio L/G is 2<L/G<10, and the most preferable range is 3<L/G<10.
The cavity portion is, for example, formed by a press forming process utilizing a press pattern with a projected portion. The cavity portion may also be formed into a multiple step structure.
Alternatively, the cavity portion may be provided with a semiconductor chip mount portion for mounting semiconductor chip, which is formed by hollowing the cavity portion out further. A depth of the semiconductor chip mount portion which has been hollowed out is preferably larger than a thickness of a semiconductor chip to be mounted therein.
Furthermore, a height of a ramp between the external connection terminal portion disposed on the substrate surface and the internal connection terminal portion disposed inside of the cavity portion may be preferably not less than 0.05 mm in the semiconductor chip package substrate and the semiconductor device according to the present invention.
The terminals of the semiconductor chip mounted inside of the cavity portion and the internal connection terminal portions are wire-bonded, or, directly connected by a face-down bonding.
Furthermore, the wiring in th
Fukutomi Naoki
Kida Akinari
Naoyuki Susumu
Wakashima Yoshiaki
Hitachi Chemical Co. Ltd.
Pennie & Edmonds LLP
Wojciechowicz Edward
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