Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-06-02
2002-11-12
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S055000, C345S085000, C345S100000, C345S108000, C345S204000, C348S750000, C348S770000
Reexamination Certificate
active
06480177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to display systems using spatial light modulators, and more particularly to the organization of display elements on the SLM and to methods of addressing the display elements with data.
2. Background of the Invention
Display systems based on spatial light modulators (SLMs) are increasingly used as alternatives to display systems using cathode ray tubes (CRTs). SLM systems provide high resolution displays without the bulk and power consumption of CRT systems.
SLMs take many forms, but one particular type is the array SLM. The array typically comprises an x-y grid of individually addressable elements, which correspond to the pixels of the image that they generate. Generally, pixel data is displayed by loading memory cells connected to the elements. The elements maintain their on or off state for controlled display times. The array of display elements may emit or reflect light simultaneously, such that a complete image is generated by addressing display elements. Examples of SLMs are liquid crystal displays (LCDs), digital micromirror devices (DMDs) and actuated mirror arrays (AMAs), both which have arrays of individually driven display elements.
Pulse-width modulation (PWM) techniques allow the system to achieve intermediate levels of illumination, between white (on) and black (off). The basic PWM scheme involves determining the rate at which images are to be presented to the viewer. This establishes a frame rate and a corresponding frame period.
Then, the intensity resolution for each pixel is established. In a simple example that assumes n bits of resolution, the frame time is divided into 2
n
−1 equal time slices. For a 33.3 millisecond frame period and n-bit intensity values, the time slice is 33.3/(2
n
−1) milliseconds. Pixel intensities are quantized, such that black is 0 time slices, the intensity level represented by the LSB is 1 time slice, and maximum brightness is 2
n
−1 time slices. Each pixel's quantized intensity determines its on-time during a frame period. The viewer's eye integrates the pixel brightness making the image appear the same as one generated with analog levels of light.
For addressing SLMs, use of PWM results in the data being formatted into “bit-planes,” each bit-plane corresponding to a bit weight of the intensity value. If each pixel's intensity is represented by an n-bit value, each frame of data has n bit-planes. The bit-plane representing the LSB of each pixel is displayed for 1 time slice, whereas the bit-plane representing the MSB is displayed for 2
n /
2 time slices. A time slice is only 33.3/(2
n
−1).milliseconds, so the SLM must be capable of loading the LSB bit-plane within that time. The time for loading the LSB bit-plane is the “peak data rate.” U.S. Pat. No. 5,278,652, entitled “DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System,” assigned to Texas Instruments Incorporated describes various methods of addressing a DMD in a DMD-based display system. These methods concern loading data at the peak data rate. In one method, the time for the most significant bit is broken into smaller segments so that loading for less significant bits can occur during these segments. Other methods involve clearing the display elements and using extra “off” times to load data.
Another approach is divided reset that involves dividing up the array of elements into reset blocks, which can be done far more easily than redesigning the entire control circuitry as in the split reset approach. Each reset block is reset to react to its new data independently, allowing the addressing circuitry underneath it to be handled in blocks, rather than as the entire array.
An embodiment of divided reset is phased reset, which involves resetting each block independently, “phasing” the data through the frame time, allowing more time for addressing and display for each block. This leads to better brightness and reduction of artifacts, since more time is used and the entire device is not reset at once. However, it can be extremely complicated when it interferes with the movement of the data to each element.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of addressing a spatial light modulator. The modulator comprises an array of individually controllable elements. The array is divided up into blocks, each block having its own reset, which allows each block to operate independently of the other blocks within a frame time. Operating each independently allows the peak data rate to be reduced. In order to allow each block to be operated independently, the address voltage is divided up to be operated by block as well. In one embodiment of the invention, logic circuitry determines which blocks require stepped address voltage and the row address for applying the address voltage is decoded.
It is an advantage of the invention in that it allows use of all of the advantages of divided reset for artifact reduction and increased brightness while eliminating problems from that process.
It is a further advantage of the invention in that it provides full range of control of the elements of the array.
It is a further advantage of the invention in that it reduces wear on the device.
REFERENCES:
patent: 5285407 (1994-02-01), Gale et al.
patent: 5548301 (1996-08-01), Kornher et al.
patent: 5581272 (1996-12-01), Conner et al.
patent: 5612713 (1997-03-01), Bhuva et al.
patent: 5657036 (1997-08-01), Markandey et al.
patent: 5673060 (1997-09-01), Blaxtan et al.
patent: 5686939 (1997-11-01), Millward et al.
patent: 5745193 (1998-04-01), Urbanus et al.
patent: 6008785 (1999-12-01), Hewlett et al.
patent: 6034660 (2000-03-01), Millward et al.
patent: 6057816 (2000-05-01), Eckersley
Chu Henry
Doherty Donald B.
Huffman James D.
Brill Charles A.
Hjerpe Richard
Tran Henry N.
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