Patent
1994-03-30
1994-11-29
LaRoche, Eugene R.
395725, G06F 1200
Patent
active
053697545
ABSTRACT:
A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.
REFERENCES:
patent: 5214776 (1993-05-01), Bagnoli
patent: 5297103 (1994-03-01), Higuchi
Fandrich Mickey L.
Gould Geoffrey A.
Rozman Rodney R.
Yarlagadda Chakravarthy
Intel Corporation
LaRoche Eugene R.
Zarahian A.
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