Block redundancy implementation in heirarchical RAM'S

Details Block redundancy implementation in heirarchical RAM'S Block redundancy implementation in heirarchical RAM'S

2007-02-13

2007-02-13

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S200000, C365S239000, C365S240000, C365S230030

Reexamination Certificate

active

10729405

ABSTRACT:
The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.

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