Block pseudo-noise generating circuit

Details Block pseudo-noise generating circuit Block pseudo-noise generating circuit

1999-09-23

2001-08-28

Pham, Chi (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C714S738000

Reexamination Certificate

active

06282230

ABSTRACT:

STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to code division multiple access (CDMA) communications systems and, more particularly, to a state generator circuit for generating a block of pseudo-noise chips having an arbitrary offset from an initial state.
2. Description of the Related Art
Present code division multiple access (CDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique code. This unique code is matched with a code of a selected receiver to determine the proper recipient of a data signal. Base stations in adjacent cells or transmit areas also have a unique pseudorandom noise (PN) code associated with transmitted data. This PN code is typically generated by a linear feedback shift register (LFSR), also known as a linear sequence shift register (LSSR), and enables mobile stations with the cell to distinguish between intended signals and interference signals from other base stations. Identification of a PN code requires that the mobile station correctly identify an arbitrary part of the received PN sequence. The identification is frequently accomplished by a correlation of a locally generated PN sequence with the PN sequence received from the base station. The sliding window algorithm often requires the mobile station to efficiently calculate multiple offsets from the LFSR to match the received sequence.
FIG. 1
illustrates a four-stage LFSR
10
; in most applications, a much larger circuit, for example, a 40-stage LFSR, would be used to generate the pseudo-noise sequence. In the illustrated embodiment, a clock signal is used to clock delay flip-flops
12
,
14
,
16
and
18
. The output, q
1
, of stage
12
is coupled to an input of exclusive-or gate
20
, along with the output, q
4
, of flip-flop
18
. The output of exclusive-or gate
20
is connected to the input of flip-flop
14
. The output, q
2
, of flip-flop
14
is coupled to the input of flip-flop
16
. The output, q
3
, of flip-flop
16
is coupled to the input of flip-flop
18
. The output of flip-flop
18
is the PN signal.
Table 1 illustrates the sequence of bits in the LFSR
10
, starting from an arbitrary initial state of “1100”.
TABLE 1
LFSR States
State
q1
q2
Q3
q4
1
1
1
0
0
2
0
1
1
0
3
0
0
1
1
4
1
1
0
1
5
1
0
1
0
6
0
1
0
1
7
1
1
1
0
8
0
1
1
1
9
1
1
1
1
10
1
0
1
1
11
1
0
0
1
12
1
0
0
0
13
0
1
0
0
14
0
0
1
0
15
0
0
0
1
1
1
1
0
0
Accordingly, the output of the circuit
10
, assuming an initial state of “1100” is “001101011110001 . . . ” which will repeat indefinitely. The PN sequence will vary depend upon which of the intermediate outputs (q
1
-q
3
) is connected to an exclusive-or gate
20
along with the output of the LFSR (q
4
). For example, if q
2
and q
4
were coupled to the exclusive-or gate
20
, the output sequence would change. The output PN sequence of a 40-stage LFSR would repeat every 2
40
-1 bits (or “chips”). In some cases, a “
0
” is inserted into the sequence in order to produce an even 2
40
bit sequence.
As stated above, it is often useful to shift a known number of bits in a PN sequence, for example, in a sliding window algorithm. U.S. Pat. No. 5,228,054 to Rueth et al, which is incorporated by reference herein, illustrates an arbitrary offset circuit for an LFSR using a mask circuit in combination with a w-bit LFSR. The mask circuit produces the desired offset in response to a mask signal. A particular problem with generation of the mask signal concerns the number of masks which would be needed in an implementation of a larger LFSR. The storage needed for the masks would create problems in many devices, such as mobile handsets, where power conservation is extremely important.
Therefore, a need has arisen for a high-speed method and apparatus for generating in offset in a PN sequence.
BRIEF SUMMARY OF THE INVENTION
In the present invention, a block of sequence bits within a pseudo-noise sequence is defined using by a desired location of a block with a pseudo-noise sequence. A known state vector is multiplied by a matrix corresponding to the offset between said known state vector and said desired location to generate an offset state vector in Fibonnaci form. A plurality of sequential bits are obtained from said offset state vector which define the block of pseudo-noise bits.
The present invention provides significant advantages over the prior art. First, after a single matrix multiplication, an entire block of sequence bits can be generated without further calculations or shifts, insofar as the block length is equal to or less than the length of the LFSR. Second, if the length of the block is less than the length of the LFSR, the offset calculation can be performed to allow shifting of the block without further calculations. Third, if the block length is greater than the length of the LFSR, the extra bits can easily be generated using one or more predetermined masks.


REFERENCES:
patent: 5228054 (1993-07-01), Rueth et al.
patent: 5758104 (1998-05-01), Gujral et al.
patent: 5926070 (1999-07-01), Barron et al.

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