Pulse or digital communications – Equalizers
Reexamination Certificate
1999-10-07
2003-06-24
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
C375S296000, C333S02800T
Reexamination Certificate
active
06584149
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to transmission of high data rate signals and more particularly to providing equalization to high data rate signals through a dispersive medium in computer and networking equipment.
BACKGROUND OF THE INVENTION
In the past, various equalization techniques have been used in the telecommunications industry to overcome transmission signal loss where digital signals are transmitted over long-distance cable. These techniques had to rely on complex and expensive equipment at both ends of a communication channel, but were feasible because the costs of the transmission lines were much more than the costs of the equipment at each end.
In the computer and networking industry, transmission losses have started to become a greater problem with the increase of data transmission speeds from megabytes per second to gigabytes per second. Although the distances in computers, for example between processors and memory, are very short, the high speeds cause high transmission signal loss. Unfortunately, the solutions used in the telecommunications industry are too expensive to be used in the computer industry, not only because of the equipment required at both ends of the transmission line, but because of the hundreds of channels required out of even a single integrated circuit of the hundreds of integrated circuits which may be involved in a multiprocessor system.
Equalization is one technique that has been used in the past is to provide an increased digital signal representing a 1 so that when it degrades through the transmission line, the degraded signal can still be identified as a “1” instead of a “0”. However, as signal speeds increase, the output signal starts to have a long “tail” due to dispersion in the channel. This long tail causes intersymbol interference that makes it difficult to properly identify the “1's” and “0's”.
One method of reducing the long tail is to send a sequence of negative pulses following the initial “1” signal. The magnitudes of the subsequent negative pulses can be easily calculated by measuring the output response. This technique is called digital equalization.
In one digital equalization technique, after the original signal bit, five subsequent negative bits of decreasing amplitude are sent out to remove the long tail in the output. It has been determined that the first negative bit is more significant and should have a greater negative amplitude than the remaining four bits. However, the remaining four bits cannot simply be eliminated because their combined effect is still large. These four bits help reduce the low frequency wander of the signal. In an actual circuit implementation, each negative bit has to be generated by a high-speed driver circuit connected to the output. While effective, this approach tends to be very costly.
A solution which would provide effective and inexpensive digital equalization has long been sought but has long eluded those skilled in the art.
DISCLOSURE OF THE PRESENT INVENTION
The present invention provides a block-mode equalization system for digital equalization in which a “1” bit pulse is followed by a significant negative bit and less significant negative bit pulses as a group with a lower bit rate. The magnitude of the grouped bit pulses, or block of equalization bit pulses, can be the average value of the individual bits to produce a clean output waveform. Since the block compensates for the lower frequency response of the channel, its effectiveness is not sensitive to the exact location of the pulses. This makes it possible to align the block in a wide pulse. This further means that when data multiplexing is involved in driver circuitry for the signal transmitter, the block can be generated from a lower frequency clocked domain before the multiplexing without burdening the high frequency side of the driver circuitry.
The present invention provides a block-mode equalization system for digital equalization in which a “1” bit pulse is followed by a significant negative bit and less significant negative bit pulses as a multiple groups with a lower bit rate. The magnitude of the grouped bit pulses, or blocks of equalization bit pulses, can be the average value of the individual bits to produce a clean output waveform. Since the block compensates for the lower frequency response of the channel, its effectiveness is not sensitive to the exact location of the pulses. This makes it possible to align the blocks in wide pulses having decreasing magnitudes and increasing durations. This further means that when data multiplexing is involved in driver circuitry for the signal transmitter, the block can be generated from a lower frequency clocked domain before the multiplexing without burdening the high frequency side of the driver circuitry.
REFERENCES:
patent: 4374426 (1983-02-01), Burlage et al.
patent: 6266379 (2001-07-01), Dally
Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, & Tomas H. Lee,“A 0.4-um CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link TRansmitter”, IEEE Solid-State Circuits, vol. 34, No. 5, May, 1999,pp. 580-585.*
W.J.Dally and J. Poulton, “Transmitter Equalization for 4 Gb/s Signaling,” in Proc. Hot Interconnects Symp., Aug. 1996, pp.29-39.*
Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, and Thomas H. Lee, “A 0.4-um CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter”, IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May, 1999, pp. 580-585.
W.J. Dally and J. Poulton, “Transmitter Equalization for 4 Gb/s Signaling,” in Proc. Hot Interconnects Symp., Aug. 1996, pp. 29-39.
Chin Stephen
Hewlett-Packard Development Company L.P.P.
Yeh Edith
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