Block-level wordline enablement to reduce negative wordline stre

Details Block-level wordline enablement to reduce negative wordline stre Block-level wordline enablement to reduce negative wordline stre

1997-02-06

1998-10-06

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular connection

36518529, G11C 1600

Patent

active

058187642

ABSTRACT:
A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.

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