Block erasable nonvolatile memory device

Details Block erasable nonvolatile memory device Block erasable nonvolatile memory device

1993-03-05

1994-12-06

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36523003, 36523008, G11C 1134, G11C 700

Patent

active

053717023

ABSTRACT:
In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.

REFERENCES:
patent: 5043942 (1991-08-01), Iwata
patent: 5050125 (1991-09-01), Momodomi
patent: 5065364 (1991-11-01), Atwood
patent: 5241510 (1993-08-01), Kobayashi

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