Block decoded redundant master wordline

Details Block decoded redundant master wordline Block decoded redundant master wordline

1994-06-30

1995-08-29

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, 36523006, G11C 700

Patent

active

054466989

ABSTRACT:
According to the present invention, defective element(s), such as a faulty local wordline, of an integrated circuit memory device may be selectively replaced with redundant element(s) in an efficient and flexible manner that does not require replacement of all elements associated with a master element of the memory device, thereby increasing the efficiency with which faulty elements of the memory device may be replaced. For a SRAM having a plurality of blocks, this is accomplished by combining defective block information as well as defective element information, such as bad row information, in the redundant global wordline control circuitry of the device. Then, the "normal" global wordline associated with a faulty local wordline is selectively disabled and a redundant global wordline is selectively enabled, upon detection of the address of the faulty local wordline. The normal global wordline can be enabled when the address corresponds to a non-faulty local wordline.

REFERENCES:
patent: 4807191 (1989-02-01), Flannagan
patent: 5257229 (1993-10-01), McClure et al.
patent: 5371712 (1994-12-01), Oguchi et al.

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