Block buffer for instruction/operand caches

Details Block buffer for instruction/operand caches Block buffer for instruction/operand caches

1992-02-24

1995-06-06

Harvey, Jack B.

395375, G06F 1300

Patent

active

054230160

ABSTRACT:
A method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read cache miss condition. A transfer of the eight word block containing the requested data element is initiated from the memory system beginning with the 72 bit double word containing the requested data element. The eight word block of data is placed into a block buffer upon being received by the instruction processor. The instruction processor is permitted to resume instruction execution and access to the cache memory as soon as the requested data element has been received by the block buffer. The eight word data block is transferred from the block buffer to cache memory at the next read cache miss condition. The block buffer has a no save designator for block transfers and other accesses for which near term subsequent access to buffered data is unlikely. Data designated no save is not transferred from the block buffer to the cache memory.

REFERENCES:
patent: 3806888 (1974-04-01), Brickman et al.
patent: 4189770 (1980-02-01), Gannon et al.
patent: 4189772 (1980-02-01), Liptay
patent: 4225922 (1980-10-01), Porter
patent: 4354232 (1982-10-01), Ryan
patent: 4433374 (1984-02-01), Hanson et al.
patent: 4437149 (1984-03-01), Pomerene et al.
patent: 4646233 (1987-02-01), Weatherford et al.
patent: 4851993 (1989-07-01), Chen et al.
patent: 4888679 (1989-12-01), Fossum et al.
patent: 4905188 (1990-02-01), Chuang et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5025366 (1991-06-01), Baror
patent: 5027270 (1991-06-01), Riordan et al.
patent: 5201041 (1993-04-01), Bohner et al.
patent: 5202972 (1993-04-01), Gusefski et al.
patent: 5247639 (1993-09-01), Yamahata
patent: 5261066 (1993-11-01), Jouppi et al.

Affiliated with

Also associated with

Rating

Block buffer for instruction/operand caches does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Block buffer for instruction/operand caches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Block buffer for instruction/operand caches will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-994186