Block arrangement for semiconductor memory apparatus

Details Block arrangement for semiconductor memory apparatus Block arrangement for semiconductor memory apparatus

2001-05-29

2003-05-06

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S149000

Reexamination Certificate

active

06560159

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to internal wiring of a semiconductor memory apparatus and more particularly to a semiconductor memory apparatus having a memory cell array divided into a plurality of n-blocks where n is not a power of 2.
BACKGROUND OF THE INVENTION
A DRAM (dynamic random access memory) is an example of a conventional semiconductor memory device. A DRAM has an array of memory cells. Each memory cell stores one bit of data. A DRAM cell is made up of a cell transistor and a cell capacitor. The cell capacitor stores data and the cell transistor provides an access path to the data on the cell capacitor. The cell capacitor stores data by either the presence or absence of charge on the capacitor in accordance with the stored data value.
The memory cells are arranged in a matrix of rows and columns. A word line is electrically connected to a plurality of cells in the row direction and bit lines are electrically connected to a plurality of memory cells in the column direction. A memory cell is formed at the intersection of a bit line and a word line. The cell transistor is electrically connected to a word line at a control gate. The cell transistor provides a controllable impedance path between a bit line and the cell capacitor.
When reading data from a memory cell, a word line is selected and the cell transistor provides a low impedance path from the bit line to the cell capacitor. This allows electrical charge to be transferred between the cell capacitor and the bit line. The charge sharing between the cell capacitor an the bit line provides a data signal to be placed on the bit line. The data signal is a change in the bit line potential based on the addition or removal of charge on the bit line. The magnitude of the data signal is determined by the ratio of the capacitance value of the bit line (Cd) and the capacitance value of the cell capacitor (Cs). The smaller the capacitance ratio (Cd/Cs), the larger the magnitude of the data signal placed on the bit line. This can increase the noise margin when reading data. The greater the capacitance ratio (Cd/Cs), the smaller the magnitude of the data signal placed on the bit line. This can decrease the noise margins when reading data. For these reasons, it is desirable to reduce the capacitance of the bit line so that the capacitance ratio (Cd/Cs) does not become too large.
In a conventional semiconductor memory device, the memory cell array is divided into a plurality of blocks. This reduces the number of memory cells connected to one bit line, thus decreasing the bit line capacitance and improving the data signal on a bit line during a read operation. When the number of blocks increases, the chip size typically increases. This can be due to the increased number of sense amplifiers required and circuitry associated with selecting a block. Thus, the number of blocks is typically determined by a maximum allowable capacitance ratio (Cd/Cs). For example, in a 256 Mbit DRAM, the memory cell array may be divided into sixteen blocks and there may be 512 memory cells connected to one bit line. This can give a capacitance ratio of approximately 7 to 8.
The block division of the memory cell array in a conventional semiconductor memory device will now be explained.
Referring now to
FIG. 1
, a 256 M-bit (megabit) synchronous DRAM (SDRAM) is set forth in a block schematic diagram and given the general reference character
100
.
SDRAM
100
includes four banks (
100
A to
100
D). Each bank has a memory density of sixty-four M-bits divided into four sub-arrays SARY. Each bank can provide 16 bits of data onto the external data pins (DQ
0
to DQ
15
). The 16 bits of data are divided into four groups. DQ
0
to DQ
3
form one group of data. DQ
4
to DQ
7
, DQ
8
to DQ
11
, and DQ
12
to DQ
15
, respectively, form the other groups. Each sub-array SARY can store bits from one group of data.
Referring now to
FIG. 19
, the bit-map illustrating the address mapping of a conventional sub-array is set forth.
The sub-array is divided into sixteen blocks (XBLK
0
to XBLK
15
) with block XBLK
0
illustrated by right cross-hatching. Each block has five-hundred-and-twelve rows of memory cells. Each block (XBLK
0
to XBLK
15
) is further divided into four small equal block sections, which can be addressed by column addresses. A block section from block XBLK
15
is illustrated by left cross-hatching. Each sub-array has a total of sixty-four block sections of memory cells. In the example illustrated in
FIG. 19
, the sixteen blocks (XBLK
0
to XBLK
15
) are selected by row addresses X
9
to X
12
as illustrated in the bit map. The four block sections in one sub-array are selected by column addresses Y
7
and Y
8
. In this way, one of the sixty-four block sections is selected according to the value of row addresses X
9
to X
12
and column addresses Y
7
and Y
8
. For example, the left cross-hatched block section is selected when row addresses X
12
to X
9
have the value (1111) and column addresses Y
8
, Y
7
have the value (11).
Sense amplifiers are provided for each block (XBLK
0
to XBLK
15
). Each bit line (or bit line pair) within a block (XBLK
0
to XBLK
15
) can be electrically connected to a sense amplifier. The bit lines are disposed in the vertical direction in the sub-array illustrated in FIG.
19
. Each bit line within a block (XBLK
0
to XBLK
15
) is connected to five-hundred-and-twelve memory cells. Each block has one-hundred-and-twenty-eight main word lines (not shown) disposed in the horizontal direction across all four block sections. Each block section has one-hundred-twenty-eight sub-word decoders. A sub-word decoder (not shown) is electrically connected to a main word line and provides four sub-word lines (not shown) in the block section. This gives a total of five-hundred-and-twelve sub-word lines in a block section.
It can be seen from the bit map of
FIG. 19
, that any of the groups of blocks (XBLK
0
to XBLK
3
; XBLK
4
to XPLK
7
; XBLK
8
to XBLK
11
; XBLK
12
to XBLK
15
) is selected according to row address X
11
and X
12
. Also, a block in a block group is selected according to row address X
9
and X
10
.
One of the one-hundred-and-twenty-eight main word lines in a block (BLK
0
to BLK
15
) is selected according to row address X
2
to X
8
. A sub-word decoder selects one of four sub-word lines according to row address X
0
and X
1
. In this example, the blocks are selected sequentially from block XBLK
0
to block XBLK
15
as the value of row addresses X
9
to X
12
(with X
9
being the less significant address) increases.
When a block (XBLK
0
to XBLK
15
) is selected according to row addresses (X
9
to X
12
), a word line within the selected block can be activated according to row addresses X
0
to X
8
. If a block (XBLK
0
to XBLK
15
) is not selected, all word lines within the block are unselected.
For example, when X
10
to X
12
have a value (000), switching row address X
9
from “0” to “1” switches between block XBLK
0
to XBLK
1
.
Referring now to
FIG. 20
, a conventional block selector is set forth in a circuit schematic diagram and given the general reference character
800
.
Conventional block selector
800
is used to select a block (XBLK
0
to XBLK
15
) in the conventional sub-array illustrated in FIG.
19
. Conventional block selector
800
has block predecoders (
810
and
820
) and a block decoder
830
. Block predecoder
810
receives and decodes row address signals X
9
and X
10
and provides predecode signals XP
10
to XP
13
to block decoder
830
. Block predecoder
820
receives and decodes row address signals X
11
and X
12
and provides predecode signals XP
20
to XP
23
to block decoder
830
. Row address signals X
9
to X
12
are provided by an address generator, such as illustrated in
FIG. 10
, which will be described later. Block decoder receives predecode signals (XP
10
to XP
13
and XP
20
to XP
23
) and provides a block select signal to each block (XBLK
0
to XBLK
15
).
Block decoder
830
has sixteen AND gates (
8301
to
8316
). Each AND gate (
8301
to
8316
) receive

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