Block architected static RAM configurable for different word wid

Details Block architected static RAM configurable for different word wid Block architected static RAM configurable for different word wid

1995-06-12

1996-11-05

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523006, 365154, 36523003, G11C 800

Patent

active

055724825

ABSTRACT:
A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory block macro (35) is built which includes a block of memory, precharge circuits, multiplexers, read/write multiplexers, and sense amplifiers. If multiple memory blocks are used a block deselect circuit (39) and row/block decoders (38) must be added to the memory block macro (35). A row and block deselection process is used in the SRAM architecture to simplify compilability and enhance speed.

REFERENCES:
patent: 5243572 (1993-09-01), Hoshizaki et al.
patent: 5247485 (1993-11-01), Ide

Affiliated with

Also associated with

Rating

Block architected static RAM configurable for different word wid does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Block architected static RAM configurable for different word wid, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Block architected static RAM configurable for different word wid will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2020387