Blanket N-LDD implantation for sub-micron MOS device manufacturi

Details Blanket N-LDD implantation for sub-micron MOS device manufacturi Blanket N-LDD implantation for sub-micron MOS device manufacturi

1994-08-12

1995-05-09

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 57, H01L 21336

Patent

active

054139457

ABSTRACT:
A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over the P-well and N-well regions is provided. The P-well region is implanted, in a substantially vertical direction, with a first conductivity-imparting dopant. Gate structures are formed over the P-well and N-well regions. A second conductivity-imparting dopant is implanted, at a large angle to the plane of the silicon substrate, that is of opposite conductivity to the first conductivity-imparting dopant, into the P-well and N-well regions, masked by the gate structures. The N-well region is implanted, in a substantially vertical direction, with a third conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. Sidewall spacers are formed on the gate structures. The P-well region is implanted, in a substantially vertical direction, with a fourth conductivity-imparting dopant, of the same conductivity as the second conductivity-imparting dopant. The N-well region is implanted, in a substantially vertical direction, with a fifth conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. The silicon substrate is heated to drive in the dopants.

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"VLSI Technology", by S. M. Sze, published by McGraw-Hill International Signapore, 1988, pp. 482-483.

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