Blanket CMOS channel stop implant employing a combination of n-c

Details Blanket CMOS channel stop implant employing a combination of n-c Blanket CMOS channel stop implant employing a combination of n-c

1988-12-19

1989-06-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 34, 437 70, H01L 21265, H01L 2708

Patent

active

048393010

ABSTRACT:
A CMOS transistor is fasbricated by forming the n-wells with both phosphorus and arsenic implants. The arsenic, with its lower diffusion coefficient, tends to concentrate near the top surface of the n-wells, with the phosphorus penetrating sufficiently to define the n-wells at the desired depth. A boron channel stop implant is later applied without masking over the n-wells. Since the arsenic implant is concentrated near the surface, the arsenic impurities overcome the effects of the boron impurities. Additional boron required for n-channel channel stop is provided by n-channel transistor punch-through implantation.

REFERENCES:
patent: 4554726 (1985-11-01), Hillenius et al.
patent: 4743563 (1988-05-01), Pfiester et al.

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