Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-12-17
2004-10-05
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S524000, C257SE21553, C257SE21564
Reexamination Certificate
active
06800917
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
—None—
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
—Not Applicable—
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor electronics, and more particularly to power semiconductor devices and methods of manufacturing such devices.
In the field of power semiconductor devices, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs), devices are often characterized according to their “safe operating areas”. Generally, the term “safe operating area” refers to operating conditions that are tolerated by a device without failure. More specifically, safe operating area can be defined as a set of maximum values of certain operating parameters. These operating parameters include maximum device current, maximum device voltage, and maximum device power dissipation. Of these parameters, all but the maximum device voltage can be influenced by changing the size of a device—larger devices generally have higher maximum current and higher maximum power dissipation. However, larger devices also occupy more area, and therefore cost more. Thus, there can be a trade-off between safe operating area and cost. As a general matter, it is desirable to maximize the safe operating area of a power device within given cost constraints to permit use of the device in a variety of applications.
It has been known to make power MOSFETs using a technology known as “silicon on insulator” or SOI. The basic characteristic of SOI technology is the presence of a buried layer of oxide forming a dielectric boundary between a bulk silicon substrate and a relatively thin silicon layer on which the active devices are formed. The benefits of SOI technology include higher device operating speed and improved electrical isolation, both owing to the use of oxide isolation rather than reverse-biased junction isolation.
Although SOI technology provides desirable benefits, it also has certain undesirable drawbacks. One of these is cost. The cost of an SOI wafer used as the starting point in device fabrication is considerably higher than the cost of non-SOI wafers. Additionally, the buried oxide layer in an SOI device is a relatively poor conductor of heat and therefore impedes vertical heat flow in the device. Thus, SOI devices generally suffer more “self heating” than do devices formed on bulk silicon, and this self heating can unduly limit the maximum permissible power dissipation for a device. Another drawback in SOI arises during the manufacturing process. During the processing of SOI wafers, impurities in the active silicon layer cannot migrate vertically across the buried oxide layer, and therefore can become trapped in the active device layer. These trapped impurities tend to collect near the surface, reducing the quality of the gate oxides and contributing to poor device performance and device failure. Special techniques are required to compensate for this tendency of impurities to be drawn to the gate oxide areas.
A technique called “partial SOI” has recently been described in the semiconductor literature. For example, a paper by Cai et al. entitled “A Partial SOI Technology for Single-Chip RF Power Amplifiers” describes the creation of an area of “partial SOI” in the drain region of a MOSFET by inserting a thick oxide layer under the drain diffusion. The thick oxide layer is obtained by first forming narrow deep trenches in the drain region and then oxidizing the lower part of the trenches laterally until the oxide completely consumes the silicon below the drain, isolating the drain from the substrate. The drain consists of multiple segments of silicon that are separated by polysilicon “fill” placed in the trenches. The drain segments are electrically interconnected by a metal drain contact extending across the width of the device. The channel, source, and sinker regions of the MOSFET remain located on bulk silicon. The paper states that the resulting device has reduced drain-substrate capacitance and reduced leakage, providing for higher power gain and higher ‘power-added efficiency’ in this RF device.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, semiconductor devices and related manufacturing methods are disclosed that address some of the shortcomings of the prior art as discussed above. In particular, the disclosed semiconductor devices obtain many of the advantages of traditional SOI-based devices, such as relatively high speed and good electrical isolation, without suffering the above-described drawbacks to the same degree as traditional SOI devices. Additionally, the disclosed devices and methods offer different advantages from those offered by the approach of “partial SOI” as described in the above-referenced paper of Cai et al.
A disclosed semiconductor device includes an elongated semiconductor element formed in a planar semiconductor substrate such as a semiconductor wafer. The semiconductor element is isolated from a surrounding conductive region of the semiconductor substrate by a buried oxide layer and side oxide layers. The oxide isolation imparts SOI-like characteristics to the device, including excellent electrical isolation. In one embodiment, the semiconductor element has a “blade” shape, extending relatively deeply into the semiconductor substrate while being relatively narrow in the horizontal direction perpendicular to its long axis.
The disclosed device further includes a polysilicon “post” disposed at one end of the semiconductor element. A sidewall of the post is in contact with a conductive end portion of the semiconductor element, and the bottom of the post extends through the buried oxide to contact the conductive region of the semiconductor substrate. The polysilicon post electrically connects the end of the element to the substrate. The post also provides for better thermal coupling between the semiconductor element and the semiconductor substrate than in traditional SOI devices. The post also provides for directing impurities away from the surface of the semiconductor element during wafer processing. These benefits are obtained without the need to contact the substrate from the back side.
A disclosed process for fabricating semiconductor devices employs a selective silicon-on-insulator technique including forming trenches in a semiconductor substrate; passivating the upper portion of a semiconductor element remaining between two adjacent trenches; and performing a long oxidation resulting in a buried oxide layer that isolates the semiconductor element from the underlying semiconductor substrate. After partial stripping of the passivation, a second oxidation is performed to create an insulating oxide layer on the sidewalls of the semiconductor element. Additionally, the buried oxide and sidewall oxide may be stripped at one end of the element, and a polysilicon post may be formed at the one end to create an electrical and thermal path between the one end of the element and the substrate. The post also provides a path for “gettering”, or directing surface impurities to the substrate during subsequent processing, and itself functions as a gettering site for such impurities.
The above fabrication method results in the selective creation of SOI-like areas on a semiconductor chip or wafer using standard processes, and thus provides the benefits of SOI without incurring the cost of SOI starting material. Additionally, the formation of a polysilicon post during processing provides for improved gettering during wafer processing, as well as the thermal and electrical coupling functions that are desired during device operation.
Other aspects, features, and advantages of the present invention will be apparent from the detailed description that follows.
REFERENCES:
patent: 6121661 (2000-09-01), Assaderaghi et al.
patent: 6127705 (2000-10-01), Kim
patent: 6274904 (2001-08-01), Tihanyi
Cai et al., “A Partial SOI Technology for Single-Chip RF Power Amplifiers”, IDEM 01/891, IEEE, 2001.
IME Strategic Focuses, Institute Of Microelectronics, Device -Fabrication Softwar
Bolkhovsky Vladimir
Haynie Sheldon D.
Merchant Steven L.
Pendharkar Sameer P.
Brady W. James
Fourson George
Pham Thanh V
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
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