Black box timing modeling method and computer system for...

Details Black box timing modeling method and computer system for... Black box timing modeling method and computer system for...

2011-07-19

2011-07-19

Memula, Suresh (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

Reexamination Certificate

active

07984404

ABSTRACT:
Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc. Accordingly, the method can be efficiently used for a latch-based design without re-verifying internal components of the latch-based design during an upper-level verification, thereby reducing verification time and model size.

REFERENCES:
patent: 6611948 (2003-08-01), Tyler et al.
patent: 2007/0226668 (2007-09-01), Dasdan et al.
Daga et al.; “Automated Timing Model Generation”; Jun. 14, 2002; Synopsys, Inc.; pp. 146-152.

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