BJT device configuration and fabrication method with reduced...

Details BJT device configuration and fabrication method with reduced... BJT device configuration and fabrication method with reduced...

2005-02-22

2005-02-22

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

C257S183000, C257S142000, C257S200000, C257S201000, C257S613000, C257S615000, C438S285000, C438S540000

Reexamination Certificate

active

06858887

ABSTRACT:
A BJT device configuration includes an emitter finger and via arrangement which reduces emitter finger width, and is particularly suitable for use with compound semiconductor-based devices. Each emitter finger includes a cross-shaped metal contact which provides an emitter contact; each contact comprises two perpendicular arms which intersect at a central area. A via through an interlevel dielectric layer provides access to the emitter contact; the via is square-shaped, centered over the center point of the central area, and oriented at a 45° angle to the arms. This allows the via size to be equal to or greater than the minimum process dimension, while allowing the width of the emitter finger to be as narrow as possible with the alignment tolerances still being met.

REFERENCES:
patent: 4654687 (1987-03-01), Hebert
patent: 5136349 (1992-08-01), Yilmaz et al.
patent: 5729033 (1998-03-01), Hafizi
patent: 5907165 (1999-05-01), Hamm et al.
patent: 6399971 (2002-06-01), Shigematsu et al.
patent: 6482711 (2002-11-01), Nguyen et al.

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