Boots – shoes – and leggings
Patent
1992-12-08
1993-06-22
Trans, Vincent N.
Boots, shoes, and leggings
364488, 395 54, 395600, G06F 1560, G06F 1540
Patent
active
052220290
ABSTRACT:
In a procedure for synthesizing circuit designs, a SYNTHESIZE command in a consequence portion of a rule can be used to control the creation of bit-level instances from a description of a more abstract instance whose interface consists of multi-bit signals. The `synthesize` command has a form that identifies multibit signal/part objects in the data base relative to the current multi-bit instance, which are then synthesized over the range of most-significant to least significant bit. A collection of rules, called macrorules are enclosed within a `synthesize` command. An iteration controlled by "current bit", ranging from least significant to most significant bit, ensues. At each step of the iteration, all macrorules are tested and applied if they are `true`. The macrorules can query whether the current bit is a function of the least or most significant bits. The macrorules can also establish connectivity to any signal bit relative to the current, the least significant or the most significant bit. Signals which represent numeric constants, are converted to the correct binary value for each bit of the bitwise synthesis. During this process, new signal names with bit subscripts are generated, if needed, and connections are made so that the resulting data base represents an electrically connected circuit.
REFERENCES:
patent: T935003 (1975-06-01), Linville et al.
patent: 4377849 (1983-03-01), Finger et al.
patent: 4386403 (1983-05-01), Hsieh et al.
patent: 4510616 (1985-04-01), Lougheed et al.
patent: 4554631 (1985-11-01), Reddington
patent: 4584653 (1986-04-01), Chih et al.
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4703435 (1987-10-01), Darringer et al.
"Quality of Designs from an Automatic Logic Generator (ALERT)", Friedman et al., 7th DA conference 1970, pp. 71-89.
"LORES--Logic Reorganization System", Nakamura et al., 15th DA Conference 1978, pp. 250-260.
"A New Look at Logic Synthesis", Darringer et al., 17th DA Conference 1980, pp. 543-549.
"Methods Used in an Automatic Logic Design Generator (ALERT)", Friedman et al., IEEE--Computer, vol. C-18, No. 7, Jul. 1969, pp. 593-610.
"Logic Synthesis Through Local Transformations", Darringer et al., IBM Journal, vol. 25, No. 4, Jul. 1981, pp. 272-280.
D. L. Dietmeyer, "Logic Design of Digital Systems", Allynt Bacon, Boston 1978, pp. 156-238.
Daniel et al., "CAD Systems for IC Design", IEEE Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-1, No. 1, Jan. 1982, pp. 2-11.
Trimberger, "Automating Chip Layout", IEEE Spectrum, vol. 19, No. 6, Jun. 1982, pp. 38-45.
Franco et al., "The Cell Design System", IEEE 18th Design Automation Conference, paper 12.4, 1981, pp. 240-247.
Kessler et al., "Standard Cell VLSI Design: A Tutorial", IEEE Circuits and Devices Magazine, Jan. 1985, pp. 17-34, cited in U.S. patent application Ser. No. 907,303.
C. L. Forgy, "OPS5 User's Manual," Carnegie-Mellon University (Jul., 1981).
K. J. Lieberherr, "Toward a Standard Hardware Description Language," IEEE Design & Test of Computers, vol. 2, No. 1, pp. 55-62 (Feb., 1985).
T. Saito et al., "A Rule-Based Logic Circuit Synthesis System for CMOS Gate Arrays," 23rd ACM/IEEE Design Automation Conference, Paper 34.1, pp. 594-600 (Jun. 29-Jul. 2, 1986).
A. Parker, "Automated Synthesis of Digital Systems," IEEE Design and Test of Computers, vol. 1, No. 4, pp. 75-81 (Nov., 1984).
Hooper Donald F.
Kundu Snehamay
Digital Equipment Corporation
Kozik Kenneth F.
Maloney Denis G.
Trans Vincent N.
Young Barry N.
LandOfFree
Bitwise implementation mechanism for a circuit design synthesis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bitwise implementation mechanism for a circuit design synthesis , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bitwise implementation mechanism for a circuit design synthesis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1444699