Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2000-12-28
2001-10-23
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S072000, C365S190000, C365S202000, C365S206000, C365S210130
Reexamination Certificate
active
06307768
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor devices, and more particularly, to a semiconductor memory device with bitline equalization in twisted bitline regions.
2. Description of the Related Art
Many current dynamic random access memory (DRAM) devices employ bitlines (BL) for reading and writing data to storage capacitors of memory cells. Many DRAM designs employ a bitline for each 512 memory cells (e.g., 512 bits/BL). To reduce bitline to bitline coupling effects, a bitline twist is introduced. These twists consume layout space.
Referring to
FIG. 1
, a schematic diagram of semiconductor memory bitline architecture is illustratively shown. The bitline architecture shows a memory array
10
having a plurality of bitlines
12
. Bitlines
12
are paired. Each pair of bitlines includes a bitline true (BLt) and a bitline complement (BLc). Each pair is indexed in
FIG. 1
to designate the pair, e.g., BLc
i
and BLt
i
, where i =
1
,
2
,
3
, . . . for pair number
1
, pair number
2
, etc. Each pair is coupled to a sense amplifier (SA)
14
. Every other BL pair includes a twist
16
. Twists
16
are employed to reduce bitline coupling between adjacent bitlines, i.e., a portion of BLt's and BLc's are separated from adjacent or nearby BLt's and BLc's to prevent cross-talk when the adjacent or nearby BLt's and BLc's are simultaneously activated. In one example, the layout area consumed by twists
16
includes a width of 6 times the pitch of a wordline
18
. Wordlines
18
in a region
20
are dummy wordlines, which are inactive as a consequence of twists
16
in this region. The twist region
20
has no active functionality, it merely serves to cross true and complement BL's every other BL-pair.
Because sense amplifiers
14
sense charge differences between BL's, the BL's need to be equalized after each active cycle. Equalizing transistors
22
are connected across each pair of BL's (e.g., BLc
1
and BLt
1
). Transistors
22
are activated by an equalize signal (EQU) to permit conduction between each pair of BL's before the next active cycle of the BL's. Transistors
22
are located near sense amplifiers
14
on one end of each pair of BL's
12
. The time needed to equalize the BL's, especially for long bitlines (e.g., 512 bits/BL architectures), before the next activate (ACT) command can be issued limits chip performance.
Referring to
FIG. 2
, an illustrative timing diagram is shown for employing BL's. The following signals are represented: a global clock signal (CLK), a row address strobe (RAS), a column address strobe (CAS) a write enable (WE), an address line (ADR) and an output line signal (DQ). The following command are also shown: activate (ACT), precharge (PRE), write (WRT) and read (READ). tRP (or row address strobe (RAS) to Precharge) represents the time it takes to equalize BL's before the ACT command.
Therefore, a need exists for reducing the time needed to equalize bitlines without chip layout penalty. A further need exists for a layout, which employs the inactive region caused by bitline twists.
SUMMARY OF THE INVENTION
A semiconductor device of the present invention includes a plurality of bitlines arranged in an array, the plurality of bitlines being grouped in pairs and at least some of the bitlines include a twist. A twist region is disposed along the plurality of bitlines wherein the twist region occupies layout area designated for the twists. An equalizer element is disposed in the twist region for equalizing a pair of bitlines.
In other embodiments, the equalizer element preferably includes a transistor coupled between a pair of bitlines. The device may include additional equalizer elements disposed near sense amplifiers of the plurality of bitlines, the additional equalizer elements being located outside the twist region. The additional equalizer elements preferably include transistors. The twist region is preferably centrally disposed along a length of the plurality of bitlines and the equalizer element and the additional equalizer element each equalize the pair of bitlines. The device may include a plurality of equalizer elements wherein the equalizer elements and the additional equalizer elements are enabled by a same equalize signal. The equalizer element may include a dummy component of the semiconductor device adapted to perform an equalizing function for the pairs of bitlines. The twist region may includes a longitudinal axis disposed substantially perpendicular to a length of the bitlines. The twist region may include a width perpendicular to the longitudinal axis and occupies an area of at least one wordline pitch. Every other pair of bitlines may include a twist, or all of the pairs of bitlines may include a twist.
Another semiconductor device of the present invention includes a plurality of bitlines arranged in an array, the plurality of bitlines being grouped in pairs and at least some of the pairs of bitlines include a twist. A twist region is disposed along the plurality of bitlines wherein the twist region occupies layout area designated for the twists. A first equalizer element is disposed in the twist region for equalizing a pair of bitlines. A second equalizer element is disposed in the twist region for equalizing bitlines between pairs of bitlines.
In other embodiments, the first equalizer element may include a transistor coupled between each pair of bitlines. Each pair of bitlines may include a true bitline and a complement bitline, and the second equalizer element may include a transistor coupled between two adjacent true bitlines or two adjacent complement bitlines. A third equalizer element may be disposed near a sense amplifier of the plurality of bitlines, the third equalizer element being located outside the twist region. The third equalizer element preferably includes a transistor. The first, second and third equalizer elements are preferably enabled by a same equalize signal. The twist region is preferably centrally disposed along a length of the plurality of bitlines and the first and second equalizer elements each equalize the pair of bitlines. The first equalizer element may include a dummy component of the semiconductor device adapted to perform an equalizing function for the pairs of bitlines. The second equalizer element may also include a dummy component of the semiconductor device adapted to perform an equalizing function for the pairs of bitlines. The twist region preferably includes a longitudinal axis disposed substantially perpendicular to a length of the bitlines. The twist region may include a width perpendicular to the longitudinal axis and occupy an area of at least about one wordline pitch.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5949698 (1999-01-01), Shirley
patent: 6097620 (2000-08-01), Naritake
patent: 6111774 (2000-08-01), Shirley
patent: 6163475 (2000-12-01), Proebsting
Braden Stanton C.
Infineon Technologies Richmond LP
Tran Andrew Q.
LandOfFree
Bitline twist with equalizer function does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bitline twist with equalizer function, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bitline twist with equalizer function will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2609384