Bitline transistor architecture for flash memory

Details Bitline transistor architecture for flash memory Bitline transistor architecture for flash memory

2008-01-15

2008-01-15

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C257S401000, C365S051000, C365S063000

Reexamination Certificate

active

11339092

ABSTRACT:
A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

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