Bitline segmentation in logic arrays

Details Bitline segmentation in logic arrays Bitline segmentation in logic arrays

1989-09-05

1991-06-11

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, G11C 1140

Patent

active

050238370

ABSTRACT:
The memory array circuit this invention provides connection of segmented bitlines to bitline decoding circuitry while, at the same time, providing connection of combined wordlines wordline decoding circuitry. The segmentation and decoding connections permit faster speed of operation with minimal or no area penalty. The area penalty is avoided by driving common wordlines in each of the segments, effectively increasing the wordline pitch at the wordline decoder, while at the same time decreasing the number of wordline decodes required. The segmentation also permits location of the decoder circuit away from the signal and routing decode outputs.

REFERENCES:
patent: 4281397 (1981-07-01), Neal et al.
patent: 4301518 (1981-11-01), Klaas
patent: 4387447 (1983-06-01), Klaas et al.

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