Bitline pull-up circuit operable in a low-resistance test mode

Details Bitline pull-up circuit operable in a low-resistance test mode Bitline pull-up circuit operable in a low-resistance test mode

1991-11-19

1993-10-05

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307568, 307475, 307443, 36518911, 365201, H03K 301, H03K 1716

Patent

active

052508544

ABSTRACT:
A method and apparatus for raising bitlines selectively to desired voltage levels. The circuit of the invention can be controlled to operate either in a first mode (for raising the bitlines selectively to relatively low voltage levels) or in a second mode (for raising the bitlines to desired higher voltage levels). The circuit of the invention has two branches, one of which includes a first (NMOS or bipolar) transistor and preferably also one or more resistors connected in series with a terminal (other than the gate or base) of the first transistor. The second branch includes a PMOS or NMOS transistor. When the PMOS (or NMOS) transistor of the second branch is switched off, the circuit's first branch operates as a bitline pull-up circuit (for raising a bitline selectively to relatively low voltage levels). When the PMOS (or NMOS) transistor of the second branch is switched on (for example, to initiate a test mode), the second branch shunts out the first branch and raises the bitline to a higher desired voltage level.

REFERENCES:
patent: 4839865 (1989-06-01), Sato et al.
patent: 5079744 (1992-01-01), Tobita et al.
patent: 5109257 (1992-04-01), Konda
patent: 5128555 (1992-07-01), Millman
patent: 5132929 (1992-07-01), Ochii

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