Bitline latch switching circuit for floating gate memory...

Details Bitline latch switching circuit for floating gate memory... Bitline latch switching circuit for floating gate memory...

2000-06-22

2001-05-15

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090, C365S189110, C326S080000

Reexamination Certificate

active

06233177

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electrically erasable programmable floating gate memory devices and, more particularly, the present invention relates to a switching circuitry for controlling the various voltages utilized to program/erase such floating gate memory devices.
DISCUSSION OF RELATED ART
Electrically erasable programmable floating gate memory devices, such as flash memory devices, typically include an array of floating gate memory cells and associated control circuitry. Each floating gate memory cell includes a floating gate structure (e.g., polysilicon) that is surrounded by an insulation material (e.g., silicon dioxide) and located over a channel extending between a source and drain region formed in a substrate. A control gate is typically located on the insulation material over the floating gate structure. Current between the source and drain is controlled by the programmed/erased state of the floating gate structure. This programmed/erased state is determined by the number of electrons stored (captured) in the floating gate structure. The floating gate structure is erased (i.e., injected with electrons until the floating gate structure stores a net negative charge) by applying a first set of voltages to the source, drain, and control gate. This net negative charge resists source-to-drain currents during read operations. Conversely, the floating gate structure is programmed (i.e., electrons are discharged until the floating gate structure has a net positive charge) by a first set of voltages to the source, drain, and control gate. This net positive charge facilitates source-to-drain currents during read operations.
The program/erase operations of floating gate memory devices require relatively high voltage differentials (i.e., relative to read operations) to inject electrons into or discharge electrons from the floating gate structures. These programming voltages are applied to the source, drain and control gates of each floating gate structure in a predetermined pattern in order to perform the desired program or erase operation. Some floating gate memory devices utilize operation voltage schemes that include both positive (i.e., above ground) and negative (i.e., below ground) voltages to reduce the stress on chip elements. In these cases, relatively large voltage differentials are created by applying a positive voltage to one terminal of the memory cell and a negative voltage to another terminal, thereby creating large voltage potentials without requiring very large positive voltages. For example, a program operation may require a voltage equal to −8.0 V (Volts) to be applied to the control gate of a memory cell, while a read operation may require a voltage equal to −2.0 V to be applied to the control gate of the memory cell. For this reason, it necessary to provide multiple negative voltages (e.g., −8 V and −2 V) to a common node (e.g., the negative supply rail of a floating gate memory cell driver circuit).
The bitline voltages of floating gate memory devices are also selectively maintained at various voltages during program, erase, and read operations. Some of these floating gate memory devices require that the bitline be isolated (i.e., floating) during, for example, program operations. This selective isolation of the bitlines is often achieved using a PMOS pass transistor located between the column latch circuit (e.g., a bitline voltage source) and the bitlines. When the control gate of these PMOS pass transistors is maintained at 0 Volts, a programming voltage (e.g., −8 V) can be passed down associated bitlines to the source terminals of the floating gate memory cells. Conversely, when a positive voltage (e.g., +5 Volts) is applied to the control gates of the PMOS pass transistors, the bitlines are isolated (floating). A problem with this arrangement is that, when a particular program/erase operation requires the bitlines to be grounded (i.e., 0 (zero) V), this 0 V signal cannot be passed by the PMOS pass transistor due to the 0 V control gate signal (i.e., because the source is equal to the gate, the PMOS transistor is not turned on, and the bitline remains floating).
What is also needed is a method for transferring various voltage levels, including 0 V, to the bitlines of a floating gate memory device during program and erase operations.
SUMMARY OF THE INVENTION
The present invention provides an electrically erasable programmable floating gate memory device that addresses the problems discussed above.
The floating gate memory device includes a series bitline latches (i.e., PMOS pass transistors) that are connected between the floating gate memory cells and a column latch circuit. In accordance with another aspect of the present invention, the gate terminals of the bitline latches are controlled by a bitline latch (BLL) switch circuit that selectively applies either a positive voltage (e.g., +5 V) or a negative voltage signal (−2 V) to the gate terminals of the bitline latches, thereby facilitating the selective passage of 0 (zero) V during, for example, program operations. The BLL control circuit includes a pass switch circuit, a small charge pump for providing the negative voltage signal, and a discharge switch. During program operations, the charge pump is activated to generate the negative voltage signal that is passed from an input terminal of the pass switch to the gate terminals of the bitline latches. During all other operations (e.g., read or erase operations), the charge pump is turned off to conserve power, and the discharge circuit is enabled to connect the input terminal of the pass switch to ground.


REFERENCES:
patent: 5708588 (1998-01-01), Haddad et al.
patent: 5986947 (1999-11-01), Choi et al.

Affiliated with

Also associated with

Rating

Bitline latch switching circuit for floating gate memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bitline latch switching circuit for floating gate memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bitline latch switching circuit for floating gate memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2569714