Bitline hard mask spacer flow for memory cell scaling

Details Bitline hard mask spacer flow for memory cell scaling Bitline hard mask spacer flow for memory cell scaling

2005-08-09

2005-08-09

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Isolation by pn junction only

C438S526000

Reexamination Certificate

active

06927145

ABSTRACT:
The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.

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Nalamasu et al., “Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance”, Jan. 2001, Fourteenth International Conference on VLSI Design, p. 469.
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Claims from U.S. Appl. No. 10/770,245, filed Feb. 02, 2004.

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