Bitline disturb reduction

Details Bitline disturb reduction Bitline disturb reduction

1996-10-28

1999-06-15

Zarabian, A.

Static information storage and retrieval

Floating gate

Disturbance control

36518518, G11C 1134

Patent

active

059128372

ABSTRACT:
A memory is described which uses floating gate transistors as memory cells in a memory array. The memory array has blocks of memory cells coupled to a common bitline. A voltage control circuit is described which provides reference voltages for reducing voltage disturbances in non-selected memory cells while selected memory cells are being programmed.

REFERENCES:
patent: 4451905 (1984-05-01), Moyer
patent: 5077691 (1991-12-01), Haddad
patent: 5317535 (1994-05-01), Talreja et al.
patent: 5412603 (1995-05-01), Schreck et al.
patent: 5444664 (1995-08-01), Kuroda
patent: 5546339 (1996-08-01), Oyama

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