Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1999-06-17
2003-05-13
Corrielus, Jean (Department: 2631)
Pulse or digital communications
Receivers
Angle modulation
C375S343000, C375S354000, C370S503000
Reexamination Certificate
active
06563886
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a bit timing synchronization device and a method for the same applied in a radio communication system such as a car telephone system. More specifically, this invention relates to a bit timing synchronization device and a method for the same for synchronizing bit timing in a channel having a wide delay spread in digital data transmission.
BACKGROUND OF THE INVENTION
FIG. 16
is a block diagram showing a bit timing synchronization device based on the conventional technology. The bit timing synchronization device based on the conventional technology comprises a correlator
3
, a power computing circuit
4
, a maximum value detecting circuit
5
, and an averaging circuit
8
.
The correlator
3
is connected to an input terminal
1
for receiving signal and it computes a correlation power between the received signal and a known sequence. The power computing circuit
4
is connected to an output terminal of the correlator
3
and it computes the correlation power. The averaging circuit
8
is connected to an output terminal of the power computing circuit
4
and it computes a moving average according to the correlation power. The maximum value detecting circuit
5
is connected in between an output terminal of the averaging circuit and a bit timing output terminal
2
, and it computes a maximum value of the correlation power using the moving average.
Operations of the conventional bit timing synchronization device will be described below.
FIG. 17
explains the operations of the bit timing synchronization device based on the conventional technology. In
FIG. 17
, the horizontal axis indicates timing from t
0
to t
9
, while the vertical axis indicates the correlation power. In the bit timing synchronization device shown in
FIG. 16
, correlation value between a received signal and a known sequence is computed by the correlator
3
, and the correlation power is computed by the power computing circuit
4
.
In the example shown in
FIG. 17
, delay spread due to a multi-path is regarded as one bit, and the optimal bit timing is at the timing t
3
. Herein it is assumed that the maximum-likelihood sequence estimation (MLSE), which is an equalizer capable of treating a delay, for instance, up to 1 bit is applied herein (As for the MLSE, refer to G. D. Forney, Jr.: “Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference”, IEEE Trans. Inform. Theory, vol. IT-18, 3, pp. 363-378, May 1972).
When the timing corresponding to the maximum value of correlation power is detected as the bit timing there occurs a problem in the bit timing synchronization device based on the conventional technology that a delay wave having a power level higher than the power level of the direct wave is disadvantageously treated as the bit timing.
To solve this problem, a moving average for 2-bit width is computed by the averaging circuit
8
.
FIG. 18
shows output from the averaging circuit
8
. In
FIG. 18
, the value corresponding to the timing t
2
is a value obtained by adding the values corresponding to the timings t
2
and t
3
shown in FIG.
17
. Similarly, the value at the timing t
3
is the value obtained by adding the values at the timings t
3
and t
4
. In
FIG. 18
, the maximumvalue is at the timing t
3
, and this timing does not change even if the value of the direct wave (at timing t
3
in
FIG. 17
) and the delayed wave (at timing t
4
in
FIG. 17
) changes.
On the other hand, when a delay time of a delayed wave becomes longer, the MLSE is not practical for solving the problem due to its circuit complexity. In such a case, the decision-feedback sequence estimation (DFSE) which is a simplified MLSE technique is used (As for the DFSE, refer to A. Duel-Hallen and C. Heegard: “Delayed decision-feedback sequence estimation”, IEEE Trans. Commun., vol. COM-37, 5, pp. 428-436, May 1989). However, when the DFSE is used there occurs a problem that only signals around bit timing can be used.
Herein it is assumed, for instance, that the DFSE capable of treating a delay of up to 3 bits is used and the moving average value is 4 bits.
FIG. 19
shows a case where the moving average value is 4 bits. As shown in
FIG. 19
, there is a possibility that any of the three timings t
1
, t
2
, or t
3
may be detected as the bit timing. When the timing t
3
is selected as bit timing, because the DFSE can utilize a signal around this bit timing t
3
an excellent performance can be obtained. However, if the timing t
2
or t
1
are detected as the bit timing the performance of the DFSE becomes worse.
Thus, when width utilized for calculating the moving average is too wide the performance degrades. Therefore, as shown in
FIG. 20
, when the delayed wave is delayed by 5-bit then width utilized for calculating the moving average is set to 4 bits. The moving average output in this case is shown in FIG.
21
. In
FIG. 21
, the moving average has a maximum value at the timings t
5
, t
6
, t
7
and t
8
, so that the timing t
3
which is the optimal bit timing is not selected.
As described above, with the bit timing synchronization device based on the conventional technology, when the applied equalizer is MLSE, it is possible to supply excellent bit timing. However, when a sub-optimal DFSE is used, there occur, for instance, the following problems:
(1) ambiguity occurs in the bit timing detected according to a moving average and a desirable bit timing can not be detected, and
(2) when the width for obtaining the moving average is narrow, bit timing is synchronized to that of a delayed wave when signal power of the delayed wave is large, and these problems make it impossible to supply acceptable bit timing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a bit timing synchronization device which can realize high precision bit timing in a channel having a wide delay spread and a method for the same.
In the present invention, a maximum value detecting means detects a maximum value of the correlation power within a pre-determined time-range. Then, a bit timing detecting means considers this detected timing corresponding to the maximum value of the correlation power as a tentative bit timing and further, detects a timing within the pre-determined time-range and prior to this tentative bit timing at which the correlation power is equal to or more than a correlation power which can be set as desired as the bit timing for the operation of the demodulator. Thus, even if the power of the direct wave is smaller than the power of the delayed wave, bit timing for starting the operation of the demodulator can be detected from the timing of the direct wave.
In the present invention, a correlation between a received signal and a known sequence and the power of this correlation is computed. Then, a maximum value of the power within a pre-determined time-range and the timing corresponding to that maximum value of the power is computed. Timing within the pre-determined time-range is reversed to the past considering the timing corresponding to the maximum value of the power as the starting point. The correlation power successively outputted corresponding to the inverted timing is compared with a threshold value which is less that the maximum value, and a timing which is the oldest timing within the pre-determined time-range at which the value of the correlation power is larger than the threshold value is detected as the bit timing for starting the operation of the demodulator. Thus, even if the power of the direct wave is smaller than the power of the delayed wave, bit timing for starting the operation of the demodulator can be detected from the timing of the direct wave.
In the present invention, a maximum value of the correlation power within a pre-determined time-range is detected. Then, this detected timing corresponding to the maximum value of the correlation power is considered as a tentative bit timing and further, a timing within the pre-determined time-range and prior to this tentative bit timing at which the correla
Kubo Hiroshi
Okazaki Akihiro
Birch Stewart Kolasch & Birch, LLP.
Corrielus Jean
Mitsubishi Denki & Kabushiki Kaisha
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