Bit synchronizing circuit configured to obviate errors from...

Details Bit synchronizing circuit configured to obviate errors from... Bit synchronizing circuit configured to obviate errors from...

2007-07-31

2007-07-31

Kumar, Pankaj (Department: 2611)

Pulse or digital communications

Synchronizers

Reexamination Certificate

active

10391702

ABSTRACT:
A bit synchronizing circuit that provides highly reliable data transmission at a high speed is provided. The circuit facilitates testing by using a plurality of clock signals that are generated based on a reference clock signal, each of the clock signals having unique phases. The circuit selects one of the clock signals as a writing clock signal that is suitable for a clock signal for synchronizing serial data, based on a synchronous timing signal. The synchronous timing signal is generated based on an edge signal that is generated based on an edge position of serial data. The edge position is determined for a plurality of groups of the clock signals, each group including clock signals chosen every predetermined number of the clock signals.

REFERENCES:
patent: 4922441 (1990-05-01), Tsukagoshi et al.
patent: 5161228 (1992-11-01), Yasui et al.
patent: 5341468 (1994-08-01), Shiraishi et al.
patent: 5396585 (1995-03-01), Fujii et al.
patent: 5448690 (1995-09-01), Shiraishi et al.
patent: 5459822 (1995-10-01), Izawa et al.
patent: 5551019 (1996-08-01), Izawa et al.
patent: 5692163 (1997-11-01), Fukushima
patent: 5732204 (1998-03-01), Fukushima et al.
patent: 5739826 (1998-04-01), Shiraishi et al.
patent: 5742801 (1998-04-01), Fukushima et al.
patent: 6594094 (2003-07-01), Rae et al.
patent: 6760389 (2004-07-01), Mukherjee et al.
patent: 2003/0091136 (2003-05-01), Sugita
patent: 7-193562 (1995-07-01), None
patent: 8-256137 (1996-10-01), None
patent: 9-36849 (1997-02-01), None
patent: 10-247903 (1998-09-01), None
patent: 10-327136 (1998-12-01), None
patent: 2003-218843 (2003-07-01), None

Affiliated with

Also associated with

Rating

Bit synchronizing circuit configured to obviate errors from... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit synchronizing circuit configured to obviate errors from..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit synchronizing circuit configured to obviate errors from... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3771467