Bit synchronizing circuit

Details Bit synchronizing circuit Bit synchronizing circuit

2005-02-01

2005-02-01

Tran, Khai (Department: 2637)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S360000, C375S371000

Reexamination Certificate

active

06850580

ABSTRACT:
A bit synchronizing circuit used in a reception circuit for serial communication comprises a data sampling circuit for over-sampling inputted data, a change point detecting circuit for detecting a change point of the inputted data based on an output from the data sampling circuit, a change point holding circuit for changing a held value stepwise in the case where the output from the change point detecting circuit is different from the held data, a selected value setting circuit for determining which value of the data sampling circuit is to be selected based on the output of the change point holding circuit and a data selecting circuit for selecting the data from the data sampling circuit based on the output of the selected value setting circuit. It alternatively may comprise a data sampling circuit for over-sampling the bit data, a synchronizing circuit, a change point detecting circuit, and a data selecting circuit.

REFERENCES:
patent: 4393301 (1983-07-01), Svendsen
patent: 5237290 (1993-08-01), Banu et al.
patent: 5687203 (1997-11-01), Baba
patent: 5887040 (1999-03-01), Jung et al.
patent: 5909473 (1999-06-01), Aoki et al.
patent: 6081561 (2000-06-01), Julyan et al.
patent: 6266799 (2001-07-01), Lee et al.
patent: 6556640 (2003-04-01), Baba
patent: 4-189044 (1992-07-01), None
patent: 6-53950 (1994-02-01), None
patent: 7-58731 (1995-03-01), None
patent: 7-95188 (1995-04-01), None
patent: 7-193562 (1995-07-01), None
patent: 8-237117 (1996-09-01), None
patent: 9-36849 (1997-02-01), None
patent: 9-83500 (1997-03-01), None
patent: 9-181709 (1997-07-01), None
patent: 9-181713 (1997-07-01), None
patent: 9-284267 (1997-10-01), None
patent: 10-247903 (1998-09-01), None
patent: 10-271101 (1998-10-01), None
patent: 11-4218 (1999-01-01), None
patent: 11-215110 (1999-08-01), None
“Phase-Locked Loops-Design, Simulation, and Applications”, Roland E. Best,The Classical Digital PLL (DPLL), pp. 156-163, 1997.
“A CMOS Serial Link for Fully Duplexed Data Communication”, Kyeongho Lee et al.,IEEE Journal of Solid State Circuits, vol. 30, No. 4, pp. 353-364, Apr. 1995.

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