Bit synchronizer with early and late gating

Details Bit synchronizer with early and late gating Bit synchronizer with early and late gating

1979-06-21

1981-07-21

Robinson, Thomas A.

Pulse or digital communications

Spread spectrum

Direct sequence

328164, 375 95, H04L 522, H03K 500

Patent

active

042802245

ABSTRACT:
This device generates clock pulses which are synchronized with the bit data rate of an input antipodal bit pattern. The device can be used with multiple input data channels whenever such channels are synchronized, i.e., the periodicity of each channel is the same and the phase relationship between channels is fixed. For example, it can be used with QPSK modulation with two input basebands; or with biphase shift keying, frequency shift keying, or other types of modulation with only one baseband input. The circuit uses a form of delay lock loop which estimates the mean zero crossing instant of the input data stream. It compares the zero crossings with early and late gates which are generated on the basis of prior analysis of the input stream. A multiple transition detector circuit is employed when the operating environment is very noisy to inhibit the counting of multiple zero crossings during a combined early gate/late gate period.

REFERENCES:
patent: 3238459 (1966-03-01), Landee
patent: 3278684 (1966-10-01), Geraghty et al.
patent: 3289082 (1966-11-01), Shumate
patent: 3401339 (1968-09-01), Kluever et al.
patent: 3482044 (1969-12-01), Kaneko
patent: 3491202 (1970-01-01), Bailey et al.
patent: 3514702 (1970-05-01), Nahay et al.
patent: 3671875 (1972-06-01), Pento
patent: 3772600 (1973-11-01), Natali
patent: 3781696 (1973-12-01), VanLoon et al.
patent: 4105979 (1978-08-01), Kage

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