Bit synchronizer

Details Bit synchronizer Bit synchronizer

1987-04-16

1988-10-25

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

375 83, 329122, H04L 702

Patent

active

047808934

ABSTRACT:
A bit synchronizer for producing a clock signal and synchronizing the clock signal to a digital data stream. The digital data stream is used to generate first and second bit rate clocks, each of which have a clock cycle time equal to one bit time. The first bit rate clock is input to a phase lock-looped for comparison with an internally generated clock. The internally generated clock, once phase locked with the first bit rate clock, controls a sampler that decodes the digital data stream. The locally generated clock is high at the mid-point of each bit interval and thus it is input to the sampler such that the sampler samples the digital data stream for decoding at the midpoint of each bit interval. The second bit rate clock, which lags the first bit rate clock by 90.degree., is input to a phase shifter. The phase shifted signal is compared with the locally generated clock. When the locally generated clock and the shifted second bit rate clock are in phase a locked condition is indicated.

REFERENCES:
patent: 3778550 (1973-12-01), David et al.
patent: 4232387 (1980-11-01), Cottatellucci
patent: 4288874 (1981-09-01), Yamada
patent: 4355398 (1982-10-01), Cook
patent: 4387342 (1983-06-01), Grosjean
patent: 4389727 (1983-06-01), Rouffet
patent: 4635280 (1987-01-01), Smith et al.
Textbook entitled "Digital Communications by Satellite", pp. 429-438, Author, J. J. Spilker, Jr.

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