Bit synchronizer

Pulse or digital communications – Spread spectrum – Direct sequence

Patent

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Details

360 51, H04L 710

Patent

active

051114860

ABSTRACT:
A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.

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patent: 4644419 (1987-02-01), Iikuma et al.
patent: 4724493 (1988-02-01), Nakamura
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