Bit synchronization circuit and method capable of correct bit sy

Details Bit synchronization circuit and method capable of correct bit sy Bit synchronization circuit and method capable of correct bit sy

1997-01-30

1999-06-29

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

375335, 329303, H04L 706

Patent

active

059178710

ABSTRACT:
A bit synchronization circuit receives polarity-judged output signal and a level-judged output signal that are produced through demodulation of a 2-value FSK or 4-value FSK transmission signal. Flip-flop circuits and an exclusive-OR circuit generate a second sampling output by sampling and delaying the polarity-judged output signal. Flip-flop circuits and an exclusive-NOR circuit generate a third sampling signal having a given temporal relationship with the second sampling output by sampling and delaying the level-judged output signal. AND circuits supply a correction signal to a counter circuit when levels of the second and third sampling outputs and a phase signal indicating a correction period of the counter circuit satisfy a given relationship. In response to the correction signal, the counter circuit corrects its count so as to produce a clock signal having a rate that is equal to a transmission rate of the transmission signal.

REFERENCES:
patent: 5155446 (1992-10-01), Eberle et al.
patent: 5371899 (1994-12-01), Kuznicki et al.
patent: 5635914 (1997-06-01), Petreye et al.
patent: 5677681 (1997-10-01), Tanaka et al.
patent: 5781588 (1998-07-01), Abe et al.

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