Bit synchronization apparatus for recovering high speed NRZ data

Details Bit synchronization apparatus for recovering high speed NRZ data Bit synchronization apparatus for recovering high speed NRZ data

1998-08-19

2000-08-15

Tokar, Michael

Coded data generation or conversion

Digital code to digital code converters

To or from nrz codes

331 57, H03M 506, H03B 2700

Patent

active

061043265

ABSTRACT:
An apparatus for recovering high speed NRZ (non-return to zero) data is disclosed. A phase-locked loop (PLL) frequency-divides the frequency which is outputted from a voltage-controlled ring oscillator, and therefore, the physical limit of the PLL is not affected. The voltage-controlled ring oscillators are installed separately from the PLL, and the voltage-controlled ring oscillators are synchronized with the PLL in the frequency only. Further, the oscillators are phase-locked to the incoming NRZ data, and two voltage-controlled ring oscillators are enabled/disabled by the binary values of the NRZ data. Therefore, a bit synchronization is realized, and thus, the voltage-controlled ring oscillators are directly controlled by the NRZ data. Consequently, the NRZ data can be recovered up to the frequency band at which the voltage-controlled ring oscillators and a D flip flop operate.

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Benny Lai et al., "A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit", 1991 IEEE International Solid-State Circuits Conference, pp. 144-145.
K.E. Syed et al., "Gigahertz Voltage-Controlled Ring Oscillator", Electronics Letters, Jun. 5th 1986, vol. 22, No. 12, pp. 677-679.

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