Bit stream rate asynchronous digital phase-locked loop

Details Bit stream rate asynchronous digital phase-locked loop Bit stream rate asynchronous digital phase-locked loop

1993-07-27

1995-08-15

Sikes, William L.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327 1, 327141, 327 12, H03K 100, H03K 518

Patent

active

054423155

ABSTRACT:
A system and method for estimating input phase for bit cells recovered from run length limited code where the bits cells have a nominal duration allows use of sampling rate as low as the nominal data rate in an all digital phase-locked loop. For the all digital phase-locked loop, a clock generates sample cells of a fixed duration. The sample cell phase contribution corresponding to a proportion of the fixed duration to the nominal duration is calculated and added to an accumulated phase value with each successive sample cell. For each sample cell, an input phase estimate is made from the accumulated phase value and timing information for any bit cell event occurring within the sample cell. Finally the input phase estimate information is used to adjust an accumulated phase value for the next sample cell.

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patent: 5057794 (1991-10-01), Shih

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