Bit stream linear equalizer with AGC loop

Pulse or digital communications – Equalizers

Reexamination Certificate

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Details

C342S092000, C348S678000, C359S341410, C375S233000, C375S234000, C379S388030

Reexamination Certificate

active

07664170

ABSTRACT:
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit includes an AGC loop, an equalizer, and an equalizer feedback loop. The AGC loop includes a gain path and a feedback path that couples to the output of the equalizer. The equalizer feedback loop couples to the output of the equalizer and produces spectral shaping control settings that the equalizer uses to produce an equalized high-speed serial bit stream at an equalizer output.

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Chen, W Y: “A Direct Equalization Method” 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing. Speech Processing, Digital Signal Processing. Munich. vol. 3, Apr. 21-24, 1997. pp. 2505-2508, XP000735068 IEEE, New York, NY, USA ISBN: 0-8186-7920-4, Abstract, p. 2507. left-hand column. line 18-right-hand column. line 21, Figures 6.

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