Bit stream conditioning circuit having adjustable PLL bandwidth

Details Bit stream conditioning circuit having adjustable PLL bandwidth Bit stream conditioning circuit having adjustable PLL bandwidth

2008-01-22

2008-01-22

Payne, David C. (Department: 2611)

Pulse or digital communications

Transceivers

C342S151000, C355S117000, C370S395620, C379S340000, C379S398000, C398S155000, C708S323000

Reexamination Certificate

active

07321612

ABSTRACT:
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

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