Image analysis – Image compression or coding
Reexamination Certificate
1998-09-22
2001-02-06
Couso, Jose L. (Department: 2721)
Image analysis
Image compression or coding
Reexamination Certificate
active
06185339
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bit stream analyzing method and apparatus for use in a decoder circuit for a high-speed decoding of a compressed bit stream generated by way of a variable-length encoding such as a video compression and an audio compression and addition of a header information, and in particular to those which can be applied to a variable-length encoder and a stream purser having a high bit rate which requires more than speed increase of a circuit.
2. Description of the Prior Art
In a conventional compression technique for a video data and audio data, for example, the data s subjected to an arithmetic conversion and the variable-length coding, after which a header information is added, thus generating a compressed bit stream.
When analyzing a compressed bit stream thus generated through a variable-length coding and addition of a header information and decoding the variable-length code contained in the bit stream, conventionally, a single bit stream analyzing apparatus has been used for analyzing the header information and decoding the variable-length code successively. In order to increase the speed of the bit stream analysis, especially, in order to increase the speed of decoding the variable-length code, various devices have been developed on a circuit.
In the aforementioned analysis of the bit stream, in order to increase the speed of analysis of the aforementioned header information, there has been used a method to increase the processing clock and the like.
On the other hand, in the aforementioned decoding of the variable-length code, a set of processing loops are required such as insert of a bit stream into a code table, read-out of a matched code, addition to a shift amount with a barrel shifter, shift with the barrel shifter, and the like. Consequently, it is difficult to increase the processing clock, for exzample, so as to increase the speed oft he decoding processing of the variable-length code. Moreover, a variable-length code is basically a one-dimensional bit stream which should be analyzed successively starting with its starting head and cannot be processed in parallel.
SUMMARY OF THE INVENTION
It is therefore an objectd of the present invention to provide a bit stream analyzing method and apparatus enabling, without requiring a high-speed clock or a high-speed circuit technique, to enhance a processing performance in analysis of a bit stream and decoding of a variable-length code which are to be processed successively.
The aforementioned object can be achieved by the bit stream analyzing and apparatus according to the present invention for analyzing a bit stream containing a compressed encode data and specific code patterns added different between predetermined units, wherein a specific code pattern of one unit is detected and according to the detection result, the bit stream is divided into a plurality of sub streams so that the plurality of sub streams are decoded separately from each other and the plurality of sub streams which have been decoded are combined with consistensy.
That is, according to the present invention, a specific code pattern detection (such as a header information processing) is carried out by pre-reading of a bit stream and according to this detection, the bit stream is divided into a pluarality of sub streams so that the sub streams are decoded in a parallel processing, thus enhancing the processing performance. Thus, the present invention can be applied in case a bit stream can be divided with a specific code pattern (such as a header information level). In the case of MPEG, for example, a bit stream is divided for each Slice.
According to another aspect of the present invention, there is provided a bit stream analyzing method and apparatus for analyzing a bit stream containing a Huffman-coded compressed data, wherein a data in the middle of the bit stream is shifted by one bit so as to be compared with a Huffman table to detect whether a match is present and according to a result of the match detection, a boundary of a Huffman code is detected, so that a dec-ode result starting at the boundary position is combined with a decode result started at the head of the bit stream, thus enabling to achieve the aforementioned object.
That is, the present invention relates to a bit stream division of a variable-length code by a decoder, wherein a pre-read of a bit stream is carried out at a head of the bit stream and in an appropriate position of the bit stream other than the head and the bit stream is entered into a Huffman decoder table. If a match is detected with any of the Huffman table value, the variable-length code decoding is carried out in the ordinary method. If no match is detected, the data is shifted by one bit so as to again detect whether a match is present. Thus, one-bit shift is carried out until a match in a Huffman table is detected. After a match is detected, a processing identical to the ordinary processing is carried out for a variable-length code decoding and a header processing so that a bit stream is analyzed in a plurality of blocks in parallel, thus enhancing the processing performance.
As has been described above, by parallel processing of a bit stream analysis, it is possible to improve the bit stream processing performance without requiring to increase the processing block clock frequency. These years, the operation speed has been increased by development of an LSI (large-scale integrated circuit), but there is a also a strong desire for reducing the power consumption by reducing the power source voltage. The parallel processing provided by the present invention also answers to such a desire.
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Couso Jose L.
Frommer William S.
Frommer Lawrence & Haug LLP.
Sony Corporation
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