Bit steering apparatus and method for correcting errors in store

Details Bit steering apparatus and method for correcting errors in store Bit steering apparatus and method for correcting errors in store

1983-09-13

1986-08-26

Harkcom, Gary V.

Excavating

371 13, 371 38, G06F 1120

Patent

active

046086870

ABSTRACT:
In a computer system, an apparatus detects the existence of an error in data retrieved from memory, corrects the erroneous data, and takes steps to maintain the correct condition of the data. In taking these steps, when the erroneous data is corrected, the corrected data is stored in a spare portion of the memory; however, the address of the corrected data in memory is recorded in a bit steering array, a physically separate memory of much smaller size. The bit steering array stores a plurality of such addresses. When an incoming read request signal is generated, it simultaneously energizes the memory and the bit steering array. In response to the read request signal, the bit steering array develops an output signal indicative of the address of the corrected data and representative of the identity of the erroneous data. In response to the read request signal, data, including the erroneous data, is read from memory. In addition, the corrected data is read from the spare portion of the memory. However, in response to the output signal from the bit steering array, the erroneous data is replaced or exchanged with the corrected data. In the case of a double bit error, one bit is corrected in the manner just described. The other bit is corrected in an error correction code matrix, which is designed to correct single bit errors.

REFERENCES:
patent: 3222653 (1965-12-01), Rice
patent: 3633175 (1972-01-01), Harper
patent: 3868646 (1975-02-01), Bergman
patent: 4061908 (1977-12-01), de Jonge et al.
patent: 4093985 (1978-06-01), Das
patent: 4163147 (1979-07-01), Scheuneman et al.
patent: 4175692 (1979-11-01), Watanabe
patent: 4255808 (1981-03-01), Schaber
patent: 4296494 (1981-10-01), Ishikawa et al.
patent: 4310901 (1982-01-01), Harding et al.
patent: 4317201 (1982-02-01), Sedalis
patent: 4319356 (1982-03-01), Kocol et al.
patent: 4371930 (1983-02-01), Kim
patent: 4384348 (1983-05-01), Nozaki
patent: 4394763 (1983-07-01), Nagano et al.
patent: 4453248 (1984-06-01), Ryan
patent: 4456993 (1984-06-01), Taniguchi et al.
patent: 4471472 (1984-09-01), Young
patent: 4475194 (1984-10-01), La Vallee et al.
patent: 4493075 (1985-01-01), Anderson et al.
patent: 4506362 (1985-03-01), Morley
IBM Technical Disclosure Bulletin, article entitled "Dynamic Allocation of Redundant Memory Components", vol. 24, No. 9, Feb. 82, pp. 4776-4778.
IBM Technical Disclosure Bulletin, "Automatic Repair Method", J. P. Roth, vol. 10, No. 7, Dec. 1967, pp. 915-916.
IBM Technical Disclosure Bulletin, "Effective Scheme for Utilizing Partially Good Chips in Memory System", G. G-C. Liu, vol. 20, No. 8, Jan. 1978, pp. 3009-3010.
IBM Technical Disclosure Bulletin, "Storage Module Reconfiguration to Bypass Bit Failures", W. G. Bouricius, W. C. Carter, J. P. Roth & P. R. Schneider, vol. 11, No. 5, Oct. 1968, pp. 550-551.
IBM Technical Disclosure Bulletin, "Processing System", R. P. Fletcher, vol. 11, No. 5, Oct. 1968, p. 515.
IBM Technical Disclosure Bulletin, "Error Correction by Reconfiguring", J. E. Heasley, Jr., & R. F. McMahon, vol. 10, No. 10, Mar. 1968, pp. 1543-1544.
IBM Technical Disclosure Bulletin, "Logical Deletion of Portions of a Push-Down Algorithm", E. L. Allen, Jr., V. L. Blunk, E. J. Ossolinski & H. G. Weber III, vol. 12, No. 12, May 1970, pp. 2150-2151.
IBM Technical Disclosure Bulletin, "Removal of Failing Buffer Sections in a Buffer-Backing Store", M. W. Bee, W. E. Boehner, J. L. Burk & B. L. McGilvray, vol. 13, No. 2, Jul. 1970, pp. 400-402.
IBM Technical Disclosure Bulletin, "Substitute Memory Location Assignment for Faulty Locations", G. H. Smith & C. H. Wolff, vol. 12, No. 9, Feb. 1970, pp. 1441-1442.
IBM Technical Disclosure Bulletin, "Read-Only Store Patch", R. M. Correy, vol. 16, No. 12, May 1974, pp. 3841-3842.
IBM Technical Disclosure Bulletin, "Permanent Alteration of Control Programs Loaded from Read/Write Disk Stores into Volatile Control Stores", K. L. Kraft, H. H. Lampe, P. Prochazka & P. Rudolph, vol. 15, No. 11, Apr. 1973, pp. 3492-3493.
IBM Technical Disclosure Bulletin, "Read-Only Store Patch", L. Doehle, U. Maier, R. Rank, vol. 24, No. 1A, Jun. 1981, p. 130.
IBM Journal of Research and Development, "Circuit Implementation of Fusible Redundant Addresses on RAM's for Productivity Enhancement", B. F. Fitzgerald & E. P. Thoma, May 1980, pp. 291-298.
IBM Technical Disclosure Bulletin, "Substitute Memory Location Locator", G. H. Smith & C. H. Wolff, vol. 12, No. 9, Feb. 1970, pp. 1443-1444.

Affiliated with

Also associated with

Rating

Bit steering apparatus and method for correcting errors in store does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit steering apparatus and method for correcting errors in store, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit steering apparatus and method for correcting errors in store will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2316046