Bit-sliced, dual-bus design of integrated circuits

Details Bit-sliced, dual-bus design of integrated circuits Bit-sliced, dual-bus design of integrated circuits

1985-08-30

1987-02-03

Gellner, Michael L.

Boots, shoes, and leggings

G06F 1560

Patent

active

046412476

ABSTRACT:
A monolithic integrated circuit chip preferably includes a pair of data busses capable of conducting in parallel the number of signals which can be processed simultaneously by the components on the chip. Signals on the busses are carried in a time-multiplexed manner, each bus having a predetermined number of time slots. Preferably, each component on the chip is connected to one or both of the busses and is assigned a particular time slot for the bus to which it is connected. The resulting chip is of a structured, rather than a custom, design. Accordingly, it can be readily expanded or contracted in the number of signals which can be simultaneously processed. The number of components which can be included on the chip is limited only by the number of time slots available on the bus to which it is connected. By providing two busses, such common circuit elements as two-input adder/subtractors can be readily accommodated by a chip designed according to the instant invention. The bit-slice organization of the chip significantly reduces the design effort of the components connected to a bus, since a one-bit slice is merely replicated for each conductor of the bus. Ease of expansion along this dimension is achieved at virtually no cost.

REFERENCES:
patent: 4583179 (1986-04-01), Horii et al.

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