Bit-serial multipliers having low latency and high throughput

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G06F 752

Patent

active

051249413

ABSTRACT:
A fractional bit-serial multiplier includes an array of partial product generators, an array of carry-save and accumulate stages and a spill-pipe to accommodate word growth and provide the higher order product terms. Circuitry between the carry-save stages and the spill pipe is provided to give the final partial products correct weighting and to avoid use of circuitry between the partial product generators and the carry-save stages.

REFERENCES:
patent: 3582634 (1971-06-01), Bartlett
patent: 3610907 (1971-10-01), Taylor
patent: 3617723 (1971-11-01), Melvin
patent: 3737638 (1973-06-01), Esteban
patent: 3805043 (1974-04-01), Clary
Smith and Denyer, Serial Data Computation, Kluwer Academic Press, 1988, pp. 72-90.

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