Bit-serial linear interpolator with sliced output

Details Bit-serial linear interpolator with sliced output Bit-serial linear interpolator with sliced output

1998-06-29

2000-06-06

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

060731516

ABSTRACT:
Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.

REFERENCES:
patent: 3789203 (1974-01-01), Catherall et al.
patent: 4031370 (1977-06-01), Catherall
patent: 4648045 (1987-03-01), Demetrescu
patent: 4975866 (1990-12-01), Aoki et al.
patent: 5559513 (1996-09-01), Rothermel et al.
patent: 5694345 (1997-12-01), Peterson

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