Bit serial convolutional decoder for VLSI implementation

Details Bit serial convolutional decoder for VLSI implementation Bit serial convolutional decoder for VLSI implementation

1982-09-20

1985-08-20

Smith, Jerry

Excavating

371 37, G06F 1110

Patent

active

045368783

ABSTRACT:
A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x.sup.6 +x.sup.5 +x.sup.3 +x.sup.2 +1, and x.sup.6 +x.sup.3 +x.sup.2 +x+1. The architecture of the instant decoder is appropriate for implementation on a single, monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals representative of data input signals.

REFERENCES:
patent: 4015238 (1977-03-01), Davis
patent: 4087787 (1978-05-01), Acampora
patent: 4130818 (1978-12-01), Snyder
patent: 4208739 (1980-06-01), Lu et al.
patent: 4240156 (1980-12-01), Doland
patent: 4293951 (1981-10-01), Rhodes
patent: 4404674 (1983-09-01), Rhodes
Clark et al., "Error-Correction Coding for Digital Communications," Plenum Press, New York, June 1981.

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