Bit residue correction in a DLC receiver

Details Bit residue correction in a DLC receiver Bit residue correction in a DLC receiver

1989-04-27

1992-08-11

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

377 69, 377 73, 377 81, 377 44, 36471508, 370 99, G11C 1900, G06F 300, G06F 1100

Patent

active

051386410

ABSTRACT:
A data link controller receiver is disclosed that includes a series of shift registers and a bit counter that counts the number of received bits. When an end of frame character is received, the value in the bit counter which represents the bit residue is supplied to a bit adjustment counter. The bit adjustment counter is employed to control the operation of the shift register containing the bit residue during a byte adjust operation, in a manner which enables the shift register containing the bit residue to be clocked until the value in the bit adjustment counter is indicative of the number of bits in a defined byte. Accordingly, the bit residue is serially shifted until the least significant bit of the shift register is filled. In addition, a mechanism is provided for loading zeros into the shift register during the byte adjust operation.

REFERENCES:
patent: H856 (1989-02-01), Kun
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patent: 4040049 (1977-08-01), Messerschmitt
patent: 4468789 (1984-08-01), Gromen
patent: 4494194 (1985-01-01), Harris et al.
patent: 4554529 (1985-11-01), Moriyama et al.
patent: 4601056 (1986-07-01), Habitzreiter et al.
patent: 4680733 (1987-07-01), Duforestel et al.
patent: 4692859 (1987-09-01), Ott
patent: 4885584 (1989-12-01), Dalrymple
patent: 4949333 (1990-08-01), Gulick et al.

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