Bit-refreshable method and circuit for refreshing a nonvolatile

Static information storage and retrieval – Floating gate – Particular biasing

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36518512, 36518533, G11C 1606

Patent

active

057681937

ABSTRACT:
In a method and circuit for refreshing a flash memory with a memory array, data corresponding to that stored in a memory cell of the memory array is read by applying a read voltage thereto. Thereafter, an erase verify voltage lower than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on non-conduction of the memory cell and the data of the memory cell, the memory cell is selectively discharged to compensate for undesired charge gain. Subsequently, a program verify voltage higher than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on conduction of the memory cell and the data of the memory cell, the memory cell is selectively charged to compensate for undesired charge loss. A method and circuit for initiating the refresh operation automatically is also disclosed.

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