Bit rate-insensitive mechanism for transmitting integrated clock

Details Bit rate-insensitive mechanism for transmitting integrated clock Bit rate-insensitive mechanism for transmitting integrated clock

1993-12-01

1996-08-27

Chin, Stephen

Pulse or digital communications

Multilevel

Synchronized

375359, 341 70, H04L 2549

Patent

active

055508642

ABSTRACT:
A totally D.C. balanced and bit-rate independent digital clock encoding technique is applicable to a variety of digital signalling systems, including fiber optic digital signalling. Each of successive event cells of the clock signal is demarcated by clock transitions of opposite polarity, so that each clock cycle contains two event cells, one of which is redundant. For a first binary data value, such as a `0`, a pair of unmodified successive event cells of the clock signal are provided as an output. Namely, the clock signal is unaffected, so that both halves of a complete, unmodified clock cycle are reproduced `as is` as the encoded clock output. For a second binary data value, such as a `1`, an event cell is modified by inserting a pulse, of finite duration, less than the duration of the event cell, the pulse being delayed with respect to a leading clock transition of the pair of alternating, opposite clock transitions of the event cell. Since event cells are encoded in pairs, in order to provide redundancy and achieve total D.C. balance, the first pulse has a first polarity, while the second pulse has a second, complementary polarity. Because the encoding mechanism of the present invention has built-in redundancy, it readily accommodates both quality monitoring at the receiver, as well as sub-rate channel signalling.

REFERENCES:
patent: 4001578 (1977-01-01), Cook et al.
patent: 4267595 (1981-05-01), Hernandez
patent: 4888791 (1989-12-01), Barndt, Sr.
patent: 4954825 (1990-09-01), Chi
patent: 5319771 (1994-06-01), Takeda

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