Pulse or digital communications – Testing – Data rate
Patent
1995-10-27
1997-05-20
Chin, Stephen
Pulse or digital communications
Testing
Data rate
H04B 346
Patent
active
056319258
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention pertains to a process for detecting the bit rates, in particular high bit rates, of serial data streams of data terminals, the control commands of the stream beginning with uniform binary characters.
The data transmission devices according to the state of the art such as modems with the standardized AT command set, which is a standard command language for communicating with data transmission devices, usually make it possible for data to be transmitted to and from the data terminal at various transmission speeds.
Problems occur when the data transmission device must be able to detect the transmission rate used by the data terminal so that it can adjust itself to that rate. Detection is possible in principle because all the control commands from the data terminal to the data transmission device begin with uniform binary characters such as, for example, the ASCII symbol "A" (=binary 01000001) or "a" (=binary 01100001).
In a known process for detecting the bit rate, the received data stream is sampled at a multiple of the maximum bit rate to be expected and compared in software with various bit patterns. Once the bit pattern has been determined, it is then possible to make a conclusion concerning the bit rate and the binary characters received ("A" or "a"). In the known process, the entire command line must be evaluated, that is, processed in software bit for bit.
This process suffers from the disadvantages that it can be realized only for low bit rates and only with the simultaneous help of a significant amount of the processing power of the CPU present in the data transmission device. Under favorable conditions, therefore, it is possible to deal with bit rates of only up to 57,600 bits/second.
SUMMARY OF THE INVENTION
The invention is based on the task of creating a process by means of which high bit rates can be reliably detected without the imposition of excessive demands on the CPU of the data transmission device. The invention is also based on the task of providing a device for implementing the process.
The accomplishment of the task indicated is based on the idea of using hardware to solve the problem instead of software. The invention is also based on the idea that the start bit or the first bits with the value "0" (start sequence) are framed by two "1" bits, so that, by determining the duration of this start sequence, it is possible to derive the bit rate used by the data terminal.
The details of the way in which the task is accomplished are as follows: designed as a shift register which is timed at a multiple of the maximum expected bit rate (shift frequency), the duration of the first bits with the value "0" (start sequence) is measured by activation of a counting circuit; and integrated component for serial data transmission.
The delay time is equal at least to the maximum duration of the start sequence plus the length of time it takes for the CPU to program the integrated component for serial data transmission. The storage capacity of the shift register required for this purpose is at least equal to the product of the shift frequency and the maximum length of the start sequence plus the time required for programming.
The digital delay stage makes it possible for the integrated component for serial data transmission, preferably a UART (Universal Asynchronous Receiver/Transmitter) of the type normally used in microprocessor technology, to be adjusted to the expected bit rate before the data stream arrives; during the time in which the data stream passes through the delay stage, the duration of the first bit or of the first bits with the value "0" is measured, and from this measurement result, the bit rate is determined in the CPU of the data transmission device and programmed into the integrated component for serial data transmission.
The start sequence is measured by activation of a counting circuit, and the bit rate calculated from the counter status is programmed into the integrated component for serial data transmission.
Because the bit rate must be
REFERENCES:
patent: 5072407 (1991-12-01), Gutz et al.
patent: 5206888 (1993-04-01), Hiraguchi et al.
Chin Stephen
ELSA GmbH
Kim Kevin
LandOfFree
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