Bit rate adaptation circuit arrangement comprising a justificati

Details Bit rate adaptation circuit arrangement comprising a justificati Bit rate adaptation circuit arrangement comprising a justificati

1990-07-06

1992-07-21

Heckler, Thomas M.

Multiplex communications

Wide area network

Packet switching

375112, H04J 307

Patent

active

051329700

ABSTRACT:
A circuit arrangement for adapting the bit rates of two signals includes an elastic store into which the data of the first signal are written in parallel in groups of n bits and from which the data bits of the second signal are read out in parallel. A selection matrix for inserting justification bits in the second signal is connected to the output of the elastic store. Writing into the store is controlled by a write counter and read-out therefrom into the selection matrix is controlled by a read counter. A subtractor forms the difference between the counts. A justification decision circuit, which can be realized all or part in CMOS technology and is capable of bit rates of the order of 140 Mbits per second, is connected to the subtractor and the read counter so as to form a control loop for the elastic store. The justification decision circuit includes a controller which produces an output signal corresponding to a running integrated summation of the differences produced by the subtractor, and a pulse distribution circuit. The output signal of the controller controls the pulse distribution circuit to supply pulses which cause the selection matrix to insert justification bits, and cause the read counter to compensate for a difference in the bit rates of the first and second signals.

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