Bit processing utilizing a row and column ladder sequence

Details Bit processing utilizing a row and column ladder sequence Bit processing utilizing a row and column ladder sequence

1984-07-27

1987-08-18

Williams, Jr., Archie E.

Boots, shoes, and leggings

364147, G06F 900

Patent

active

046881930

ABSTRACT:
A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.

REFERENCES:
patent: 3944987 (1976-03-01), Koyanagi et al.
patent: 3969723 (1976-07-01), Kennicott
patent: 4316260 (1982-02-01), Hideshima et al.
patent: 4386403 (1983-05-01), Hsieh
patent: 4432047 (1984-02-01), Okayama
patent: 4441161 (1984-04-01), Sasaki et al.
patent: 4445169 (1984-04-01), Wakita
patent: 4449180 (1984-05-01), Ohshima
patent: 4486830 (1984-12-01), Taylor

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