Bit processing unit for performing complex logical operations wi

Details Bit processing unit for performing complex logical operations wi Bit processing unit for performing complex logical operations wi

1996-04-22

1997-12-30

Lim, Krisna

395565, G06F 752

Patent

active

057040524

ABSTRACT:
A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.

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G.B. Steven, et al., "HARP: A Parallel Pipelined RISC Processor," Microprocessors and Microsystems, vol. 13, No. 9, Nov. 1989, pp. 579-587.
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