Bit-phase aligning circuit

Details Bit-phase aligning circuit Bit-phase aligning circuit

1995-11-29

1998-07-07

Butler, Dennis M.

395552, 395558, G06F 104

Patent

active

057782148

ABSTRACT:
A bit-phase aligning circuit includes a bit-phase adjusting circuit and a synchronizing pattern detection circuit. The bit-phase adjusting circuit adjusts a phase difference between a data signal and a clock signal by adjusting a delay amount of the data signal based on a determination result signal from the synchronizing pattern detection circuit. In the synchronizing pattern detection circuit, the data signal is sampled using the clock signal so as to detect a synchronizing pattern inserted in the data signal. When the synchronizing pattern is detected, the synchronizing pattern detection circuit determines that a phase relationship between the data signal and the clock signal is proper. On the other hand, when not detected, the synchronizing pattern detection circuit determines the phase relationship therebetween to be improper. This determination result signal is fed to the bit-phase adjusting circuit where the phase difference between the data signal and the clock signal is adjusted.

REFERENCES:
patent: 4756011 (1988-07-01), Cordell
patent: 4773085 (1988-09-01), Cordell
patent: 4821296 (1989-04-01), Cordell
patent: 5081655 (1992-01-01), Long
patent: 5134636 (1992-07-01), Barucchi et al.
patent: 5278873 (1994-01-01), Lowrey et al.
patent: 5550860 (1996-08-01), Georgiou et al.
Robert R. Cordell, "A 45 --Mbit/s CMOS VLSI Digital Phase Aligner," IEE Journal of Solid-State Circuits, vol. 23, No. 2, (Apr. 1988), pp. 323-328.

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